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74ABT240CSJX

Description
IC BUFFER INVERT 5.5V 20SOP
Categorysemiconductor    logic   
File Size102KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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74ABT240CSJX Overview

IC BUFFER INVERT 5.5V 20SOP

74ABT240CSJX Parametric

Parameter NameAttribute value
logical typebuffer, reverse
Number of components2
bits per component4
input type-
Output typeThree states
Current - output high, low32mA,64mA
Voltage - Power4.5 V ~ 5.5 V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount
Package/casing20-SOIC (0.209", 5.30mm wide)
Supplier device packaging20-SOP
74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
March 1994
Revised March 2005
74ABT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Features
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT240CSC
74ABT240CSJ
74ABT240CMSA
74ABT240CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
Description
3-STATE Output
Enable Inputs
I
0
–I
7
O
0
–O
7
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
I
n
L
H
X
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
H
L
Z
© 2005 Fairchild Semiconductor Corporation
DS011664
www.fairchildsemi.com
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