74F109 Dual JK Positive Edge-Triggered Flip-Flop
April 1988
Revised September 2000
74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes
both Q and Q HIGH
Ordering Code:
Order Number
74F109SC
74F109SJ
74F109PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009471
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74F109
Truth Table
Inputs
S
D
L
H
L
H
H
H
H
H
C
D
H
L
L
H
H
H
H
H
CP
X
X
J
X
X
X
I
h
I
h
X
K
X
X
X
I
I
h
h
X
Q
H
Q
Q
H
L
H
L
Toggle
Q
L
Q
Outputs
Q
L
H
H
H
X
L
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage Level
=
LOW-to-HIGH Transition
X
=
Immaterial
Q
0
(Q
0
)
=
Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
U.L.
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Description
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.8 mA
20
µ
A/
−
1.8 mA
Q
1
, Q
2
, Q
1
, Q
2
Outputs
−
1 mA/20 mA
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F109
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
cc
= 0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
175
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
10% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Output HIGH Leakage Current
Input Leakage Test
4.75
Output Leakage
3.75
Circuit Current
I
IL
Input LOW Current
−0.6
−1.8
I
OS
I
CC
Output Short-Circuit Current
Power Supply Current
−60
11.7
−150
17.0
V
0.0
10% V
CC
2.5
V
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
Min
Max
Max
Max
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
I
OD
µA
mA
mA
mA
mA
0.0
Max
Max
Max
Max
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (J
n
, K
n
)
V
IN
=
0.5V (C
Dn
, S
Dn
)
V
OUT
=
0V
CP
=
0V
3
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74F109
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to
Q
n
or Q
n
100
3.8
4.4
3.2
3.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
125
5.3
6.2
5.2
7.0
7.0
8.0
7.0
9.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
90
3.8
4.4
3.2
3.5
8.0
ns
9.2
8.0
10.5
ns
ns
Max
MHz
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
J
n
or K
n
to CP
n
Hold Time, HIGH or LOW
J
n
or K
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
C
Dn
or S
Dn
Pulse Width LOW
Recovery Time
2.0
C
Dn
or S
Dn
to CP
2.0
ns
3.0
3.0
1.0
1.0
4.0
5.0
4.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.0
ns
1.0
1.0
4.0
ns
5.0
4.0
ns
Max
Units
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4
74F109
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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