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74ACTQ74PC

Description
IC FF D-TYPE DUAL 1BIT 14DIP
Categorysemiconductor    logic   
File Size214KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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74ACTQ74PC Overview

IC FF D-TYPE DUAL 1BIT 14DIP

74ACTQ74PC Parametric

Parameter NameAttribute value
FunctionSetup (preset) and reset
typeD type
Output typedifference
Number of components2
bits per component1
Clock frequency200MHz
Maximum propagation delay at different V, maximum CL8ns @ 5V,50pF
Trigger typepositive edge
Current - output high, low24mA,24mA
Voltage - Power4.5 V ~ 5.5 V
Current - static (Iq)20µA
Input capacitance4.5pF
Operating temperature-40°C ~ 85°C(TA)
Installation typeThrough hole
Package/casing14-DIP(0.300",7.62mm)
74ACTQ74 Quiet Series Dual D-Type
March 1993
Revised November 1999
74ACTQ74
Quiet Series Dual D-Type
Positive Edge-Triggered Flip-Flop
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q) out-
puts. Information at the input is transferred to the outputs
on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive-going
pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next
rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes
both Q and Q HIGH
Features
s
I
CC
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
4 kV minimum ESD immunity
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACTQ74SC
74ACTQ74SJ
74ACTQ74PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010920
www.fairchildsemi.com

74ACTQ74PC Related Products

74ACTQ74PC 74ACTQ74SC 74ACTQ74SJX
Description IC FF D-TYPE DUAL 1BIT 14DIP IC FF D-TYPE DUAL 1BIT 14SOIC IC FF D-TYPE DUAL 1BIT 14SOP
Function Setup (preset) and reset Setup (preset) and reset Setup (preset) and reset
type D type D type D type
Output type difference difference difference
Number of components 2 2 2
bits per component 1 1 1
Clock frequency 200MHz 200MHz 200MHz
Maximum propagation delay at different V, maximum CL 8ns @ 5V,50pF 8ns @ 5V,50pF 8ns @ 5V,50pF
Trigger type positive edge positive edge positive edge
Current - output high, low 24mA,24mA 24mA,24mA 24mA,24mA
Voltage - Power 4.5 V ~ 5.5 V 4.5 V ~ 5.5 V 4.5 V ~ 5.5 V
Current - static (Iq) 20µA 20µA 20µA
Input capacitance 4.5pF 4.5pF 4.5pF
Operating temperature -40°C ~ 85°C(TA) -40°C ~ 85°C(TA) -40°C ~ 85°C(TA)
Installation type Through hole surface mount surface mount
Package/casing 14-DIP(0.300",7.62mm) 14-SOIC (0.154", 3.90mm wide) 14-SOIC (0.209", 5.30mm wide)
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