74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs
November 1999
Revised November 2000
74LVTH646
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH646 consists of registered bus transceiver cir-
cuits, D-type flip-flops, and control circuitry providing multi-
plexed transmission of data directly from the input bus or
from the internal storage registers. Data on the A or B bus
will be loaded into the respective registers on the LOW-to-
HIGH transition of the appropriate clock pin (CPAB or
CPBA). (See Functional Description)
The LVTH646 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
The bus transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH646 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
−
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 646
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Order Number
74LVTH646WM
74LVTH646MTC
Package Number
M24B
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS012017
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74LVTH646
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
7
Description
Data Register A Inputs
Data Register A Outputs
B
0
–B
7
Data Register B Inputs
Data Register B Outputs
CPAB, CPBA
SAB, SBA
OE
DIR
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
Truth Table
(Note 1)
Inputs
OE
H
H
H
L
L
L
L
L
L
L
L
DIR
X
X
X
H
H
H
H
L
L
L
L
CPAB
H or L
X
X
CPBA
H or L
SAB
X
X
X
L
L
H
H
X
X
X
X
SBA
X
X
X
X
X
X
X
L
L
H
H
X
=
Immaterial
Data I/O
A
0
–A
7
Input
B
0
–B
7
Isolation
Input
Clock A
n
Data into A Register
Clock B
n
Data into B Register
A
n
to B
n
—Real Time (Transparent Mode)
Input
Output
Clock A
n
Data into A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
—Real Time (Transparent Mode)
Output
Input
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
Data into B Register and Output to A
n
=
LOW-to-HIGH Transition
Function
X
X
X
X
X
X
X
X
X
H or L
H or L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
Note 1:
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LVTH646
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The
select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-
management functions that can be performed.
The direction control (DIR) determines which bus will receive data when OE is LOW. In the isolation mode (OE HIGH), A
data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled,
the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be
driven at a time.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus B to Bus A
OE
L
DIR
L
CPAB CPBA SAB SBA
X
X
X
L
OE
L
DIR
H
CPAB CPBA SAB SBA
X
X
L
X
Transfer Storage
Data to A or B
Storage
OE
L
L
DIR
L
H
CPAB CPBA SAB SBA
X
H or L
H or L
X
X
H
H
X
OE
L
L
H
H
DIR
H
L
X
X
CPAB CPBA SAB SBA
X
X
X
X
L
X
X
X
X
L
X
X
3
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74LVTH646
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
O
>
V
CC
Output at HIGH State
Output at LOW State
V
V
mA
mA
mA
mA
mA
−
0.5 to
+
4.6
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
50
−
50
64
128
±
64
±
128
−
65 to
+
150
°
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
−
32
64
−
40
0
85
10
°
C
ns/V
∆
t/
∆
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
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4
74LVTH646
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
V
OL
Output LOW Voltage
2.7
2.7
3.0
3.0
3.0
I
I(HOLD)
I
I(OD)
I
I
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 6)
Note 4:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
T
A
=−40°C
to
+85°C
Min
2.0
0.8
V
CC
−
0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
0.19
5
0.19
0.19
0.2
Max
−1.2
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
Conditions
I
I
= −18
mA
V
O
≤
0.1V or
V
O
≥
V
CC
−
0.1V
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −32
mA
I
OL
=
100
µA
I
OL
=
24 mA
I
OL
=
16 mA
I
OL
=
32 mA
I
OL
=
64 mA
V
I
=
0.8V
V
I
=
2.0V
(Note 4)
(Note 5)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V
V
I
=
GND or V
CC
V
O
=
0.0V
V
O
=
3.6V
V
CC
<
V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V
Outputs Disabled
One Input at V
CC
−
0.6V
Other Inputs at V
CC
or GND
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
Min
(Note 7)
T
A
=
25°C
Typ
0.8
−0.8
Max
Conditions
Units
V
V
C
L
=
50 pF, R
L
=
500Ω
(Note 8)
(Note 8)
Note 7:
Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 8:
Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
5
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