ST72P60K2U1 datasheet, PDF - EEWORLD Datasheet

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ST72P60K2U1: DescriptionLOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI); CategoryThe embedded processor and controller Microcontrollers and processors; File Size935KB，139 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST72P60K2U1 Overview

LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)

ST72P60K2U1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFN
package instruction	6 X 6 MM, LEAD FREE, QFN-40
Contacts	40
Reach Compliance Code	compli
Has ADC	NO
Address bus width
bit size	8
CPU series	ST72
maximum clock frequency	24 MHz
DAC channel	NO
DMA channel	YES
External data bus width
JESD-30 code	S-XQCC-N40
length	6 mm
Number of I/O lines	19
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	YES
Package body material	UNSPECIFIED
encapsulated code	VQCCN
Encapsulate equivalent code	LCC40,.24SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	384
rom(word)	8192
ROM programmability	MROM
Maximum seat height	1 mm
speed	8 MHz
Maximum slew rate	13 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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ST7260xx

Low speed USB 8-bit MCU family with up to 8K Flash

and serial communications interface

Features

■

Memories

– 4 or 8 Kbytes program memory: high

density Flash (HDFlash), or FastROM with

readout and write protection

– In-application programming (IAP) and in-

circuit programming (ICP)

– 384 bytes RAM memory (128-byte stack)

Clock, reset and supply management

– Run, Wait, Slow and Halt CPU modes

– 12 or 24 MHz oscillator

– RAM Retention mode

– Optional low voltage detector (LVD)

USB (Universal Serial Bus) interface

– DMA for low speed applications compliant

with USB 1.5 Mbs (version 2.0) and HID

specifications (version 1.0)

– Integrated 3.3 V voltage regulator and

transceivers

– Supports USB DFU class specification

– Suspend and Resume operations

– 3 Endpoints with programmable In/Out

configuration

Up to 19 I/O ports

– Up to 8 high sink I/Os (10 mA at 1.3 V)

Device summary

ST7260K2

■

SO24

QFN40

(6x6)

■

– 2 very high sink true open drain I/Os (25

mA at 1.5 V)

– Up to 8 lines with interrupt capability

2 timers

– Programmable Watchdog

– 16-bit Timer with 2 Input Captures, 2

Output Compares, PWM output and clock

input

Communications interface

– Asynchronous serial communications

interface (SCI)

Instruction set

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

Development tools

– Versatile development tools including ,

software library, hardware emulator,

programming boards, HID and DFU

software layer

ST7260E2

384 (128)

ST7260E1

■

Table 1.

Features

Flash program memory -

bytes

RAM (stack) - bytes

Peripherals

Operating supply

CPU frequency

Operating temperature

Packages

ST7260K1

Watchdog timer, 16-bit timer, USB, SCI

4.0 V to 5.5 V

8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)

0 °C to +70 °C

QFN40 (6x6)

SO24

February 2009

Rev 3

1/139

www.st.com

139

Contents

ST7260xx

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7.1

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1

7.2

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2.1

7.2.2

Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/139

ST7260xx

Contents

7.3

Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.1

7.3.2

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.0.1

Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1

9.2

9.3

9.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.1

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

10.2.7

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1

12.2

12.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/139

Contents

ST7260xx

12.4

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.4.1

12.4.2

12.4.3

12.4.4

12.4.5

12.4.6

12.4.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.1

13.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

13.2.1

13.2.2

13.2.3

13.2.4

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

13.3

13.3.1

13.3.2

13.3.3

13.3.4

13.3.5

Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.1

14.2

14.3

14.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.4.1

14.4.2

14.4.3

14.4.4

14.4.5

14.4.6

14.4.7

14.4.8

DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4/139

ST7260xx

14.4.9

Contents

Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5

Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.5.1

14.5.2

14.5.3

14.5.4

Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

15.1.1

15.1.2

15.1.3

15.1.4

15.1.5

15.1.6

15.1.7

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.1.1

16.1.2

16.1.3

16.1.4

16.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

16.2

16.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16.3.1

16.3.2

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113

16.4

16.5

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

16.5.1

16.5.2

16.5.3

General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16.6

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5/139

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