Pin assignment in CLK mode (IF_SEL pin = L) is shown in below figure.
<TOP View>
TORQE2
TORQE1
TORQE0
CP+
CPOUT
MDT1
MDT0
GND
GND
GND
AGC
CP-
NC
NC
VM
34
48
MODE0
MODE1
MODE2
CLK
CW/CCW
STANDBY
ENABLE
RESET
GAIN_SEL
EDG_SEL
TESTI_1
TESTI_2
TESTI_3
LO0
LO1
MO
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
TESTO_1
47
46
45
44
43
42
41
40
39
38
37
36
35
VM
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
RS_B
RS_B
NC
OUT_B+
OUT_B+
OUT_B-
OUT_B-
OUT_A-
OUT_A-
OUT_A+
OUT_A+
NC
RS_A
RS_A
NC
16
TEST_VF
2
TESTO_2
3
TESTO_3
4
SGND
5
OSCM
6
CLIM0
7
CLIM1
8
FLIM
9
BST
10
VREF
11
IF_SEL
12
RS_SEL
13
NC
14
VCC
15
LTH
Note: Please solder the corner pad and the rear thermal pad of the QFN package, to the GND pattern of the PCB.
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2018-06-11
TB67S128FTG
4. Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Symbol
CLK mode
TESTO_1 (Note1)
TESTO_2 (Note1)
TESTO_3 (Note1)
SGND
OSCM
CLIM0 (Note1)
CLIM1 (Note1)
FLIM (Note1)
BST (Note1)
VREF
IF_SEL
RS_SEL
NC
VCC
LTH (Note1)
TEST_VF (Note1)
NC
RS_A (Note2)
RS_A (Note2)
NC
OUT_A+ (Note2)
OUT_A+ (Note2)
OUT_A- (Note2)
OUT_A- (Note2)
OUT_B- (Note2)
OUT_B- (Note2)
OUT_B+ (Note2)
OUT_B+ (Note2)
NC
RS_B (Note2)
RS_B (Note2)
NC
VM (Note2)
VM (Note2)
NC
CPOUT
CP+
CP-
GND
GND
GND
MDT0
MDT1
Serial mode
TESTO_1 (Note1)
TESTO_2 (Note1)
TESTO_3 (Note1)
SGND
OSCM
NC
NC
NC
NC
VREF
IF_SEL
NC
NC
VCC
LTH (Note1)
TEST_VF (Note1)
NC
RS_A (Note2)
RS_A (Note2)
NC
OUT_A+ (Note2)
OUT_A+ (Note2)
OUT_A- (Note2)
OUT_A- (Note2)
OUT_B- (Note2)
OUT_B- (Note2)
OUT_B+ (Note2)
OUT_B+ (Note2)
NC
RS_B (Note2)
RS_B (Note2)
NC
VM (Note2)
VM (Note2)
NC
CPOUT
CP+
CP-
GND
GND
GND
NC
NC
TEST OUT pin No.1
TEST OUT pin No.2
TEST OUT pin No.3
Logic ground pin
Internal oscillator frequency monitor and setting pin
AGC current limiter setup pin No.0
AGC current limiter setup pin No.1
AGC frequency limiter setup pin
AGC current boost setup pin
Current threshold reference pin
Interface select pin
RS mode select pin
NC pin
Internal regulator voltage monitor pin
AGC threshold setup pin
TEST monitor (3VF)
NC Pin
Ach current sense resistor connected pin /
Ach motor power ground pin
Ach current sense resistor connected pin /
Ach motor power ground pin
NC pin
Ach motor output(+) pin
Ach motor output(+) pin
Ach motor output(-) pin
Ach motor output(-) pin
Bch motor output(-) pin
Bch motor output(-) pin
Bch motor output(+) pin
Bch motor output(+) pin
NC pin
Bch current sense resistor connected pin /
Bch motor power ground pin
Bch current sense resistor connected pin /
Bch motor power ground pin
NC pin
Motor power supply input pin
Motor power supply input pin
NC pin
Pin for Charge pump
Pin for Charge pump
Pin for Charge pump
GND
GND
GND
Mixed Decay/ADMD setting pin
Mixed Decay/ADMD setting pin
Description
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2018-06-11
TB67S128FTG
Pin No.
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
CLK mode
TORQE0
TORQE1
TORQE2
AGC
NC
MODE0
MODE1
MODE2
CLK
CW/CCW
STANDBY
ENABLE
RESET
GAIN_SEL
EDG_SEL
TESTI_1 (Note1)
TESTI_2 (Note1)
TESTI_3 (Note1)
LO0
LO1
MO
Serial mode
NC
NC
NC
NC
NC
NC
NC
NC
CLK
DATA
STANDBY
LATCH
BANK_EN
NC
NC
TESTI_1 (Note1)
TESTI_2 (Note1)
TESTI_3 (Note1)
LO0
LO1
NC
Torque setting pin No.0
Torque setting pin No.1
Torque setting pin No.2
Active Gain Control setup pin
NC pin
Description
Excitation
setting pin No.0
Excitation
setting pin No.1
Excitation
setting pin No.2
Step clock input pin / Serial clock input pin
Current direction setup pin / Data input pin in serial interface
Standby pin
Motor output ON/OFF pin / Latch Enable input pin
Electrical angle initialize pin / BANK select pin
Vref Gain setting pin
CLK edge setting pin
TEST input pin No.1
TEST input pin No.2
TEST input pin No.3
Error detection flag output pin No.0
Error detection flag output pin No.1
Electrical angle monitor pin
Note1: This pin should be opened or connected to Ground.
Note2: The same name pins should be connected with PCB pattern each other.
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2018-06-11
TB67S128FTG
5. Block Diagram
MODE0
MODE1
MODE2
CLK
ENABLE
RESET
STANDBY
CW/CCW
TORQUE0
TORQUE1
TORQUE2
EDG_SEL
MDT0
MDT1
RS_SEL
GAIN_SEL
IF_SEL
AGC
CLIM0
CLIM1
FLIM
BST
LO0
LO1
MO
OSCM
CPOUT
CP+
VM
CP－
BUF_MULTI
OUT_NOD
Charge Pump
BIAS
BUF_HYS
OSC_CR
BGR
VREG_5
To analog
To logic
VCC
IN_FIL
OSC_6.4M
TSD
IREFMR_
5U
IREF
Logic
CLOCK IN Contrpl
SIRIAL IN Control
VREF
LTH
SGND
BGR
LTH_VI
DET_COMP
GAIN_AMP
U_STEP_DAC
H_EFF_DAC
U_STEP_DAC
GAIN_AMP
DET_COMP
LVSHIFT
_6BIT
IOUT_VI
ISD
ISD
SENS_ISDH
SENS_ISDL
(S285転用)
WAVE_COMP
WAVE_COMP
IOUT_VI
GND
PREDRV
SENS_ILEVEL
SENS_ISDH
SENS_ISDL
SENS_ILEVEL
PREDRV
VM
OUT_A
(HSW)
OUT_B
(HSW)
VM
OUT_A+
RS_A
OUT_A-
OUT_B-
RS_B
OUT_B+
Note: Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purpose.
Note: All the grounding wires of the TB67S128FTG should run on the solder mask on the PCB and be externally terminated at only one point. Also, a grounding method should be
considered for efficient heat dissipation. Careful attention should be paid to the layout of the output, VM and GND traces, to avoid short circuits across output pins or to the power
supply or ground. If such a short circuit occurs, the device may be permanently damaged. Also, the utmost care should be taken for pattern designing and implementation of the
device since it has power supply pins (VM, RS line, OUT line, and GND) through which a particularly large current may run. If these pins are wired incorrectly, an operation error
may occur or the device may be destroyed. The logic input pins must also be wired correctly. Otherwise, the device may be damaged owing to a current running through the IC
that is larger than the specified current. Careful attention should be paid to design patterns and mountings.
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