532AC000335DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> 532AC000335DG

532AC000335DG: DescriptionDUAL FREQUENCY XO, OE PIN 2; CategoryPassive components; File Size457KB，12 Pages; ManufacturerSilicon Laboratories Inc

Download Datasheet Parametric View All

532AC000335DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	532AC000335DG	-	-	View	Buy Now

532AC000335DG Overview

DUAL FREQUENCY XO, OE PIN 2

532AC000335DG Parametric

Parameter Name	Attribute value
type	XO (Standard)
Frequency - Output 1	500MHz
Frequency - Output 2	1GHz
Frequency - Output 3	-
Frequency - Output 4	-
Function	enable/disable
output	LVPECL
Voltage - Power	3.3V
frequency stability	±7ppm
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	121mA
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
high	0.071"（1.80mm）
Package/casing	6-SMD, no leads
Current - Power (disabled) (maximum)	75mA

Preview

Download Datasheet

View All

Si532

EVISION

U A L

REQUENCY

R Y S TA L

SCILLATOR

(X O )

(10 M H

Z TO

1 . 4 G H

)

Features

Available with any-frequency output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



Two selectable output frequencies



3 generation DSPLL with superior



jitter performance



3x better frequency stability than

SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation



Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si532 is

available with any-frequency output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is

required for each output frequency, the Si532 uses one fixed crystal

frequency to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The Si532 IC

based XO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output format, and temperature stability.

Specific configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

CLK–

CLK+

(LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

(CMOS)

Fixed

Frequency

Any-frequency

10–1400 MHz

DSPLL

Clock

Synthesis

GND

Rev. 1.4 6/18

Si532

Recommended Resources

Negative resistance dielectric oscillator and equivalent circuit

Power outage emergency lights (2)

Use LC172 to make novel voice-controlled music lanterns

High-pass active filter circuit using LM110

Baby sleeping cold notification device

Let's give this section a catchy name.: Haha, the pool is really unfathomable. A bubble that appears inadvertently can attract everyone's enthusiastic attention.Recently, the issue of the number of forum posts has attracted great attention....; tiankai001 Talking

Notes on using 51 external bank: Recently, I have been using CME_M5 from JINGWEI YaGe, which is a FPGA+51 chip. When using 51, the internal resources are not enough, so I used Code bank. Currently, 8 banks are used, but the program s...; hhakex 51mcu

Do you have an 802.11a wireless communication module?: I want to use 802.11a module to make something recently, but I don't know what type of module can be used in S3C6440 or other ARM platforms. I searched on Taobao and found almost all of them are minip...; ghoulich RF/Wirelessly

Attribute issues of medium-length control in Cadence: [font=Tahoma,]When performing equal length control routing, the routing of the same net needs to be controlled. But now my problem is that the equal length of Pin to Pin is directly generated in the c...; HJobe PCB Design

A well-known Beijing communications company is recruiting Video Codec algorithm engineers: Video Codec Algorithm Engineer 15K-20K or so Job Responsibilities: Design, port, optimize and implement video codec algorithms for different platforms. Qualifications: 1. Master's degree or above, maj...; 安德Tyler Recruitment

Help: Strange problem with MIC3390 network card driver, please help experts!!!: Hardware: Advantech MIC3390 cpu board, network card gei82573. I use CF card to boot (SATA seems to be not supported by BSP. The current situation is that there are always errors and I don’t have time ...; lzj000008 Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components