NCP59744
3.0 A, Dual-Rail Very
Low-Dropout Linear
Regulator with
Programmable Soft-Start
The NCP59744 is dual−rail very low dropout voltage regulator that
is capable of providing an output current in excess of 3.0 A with a
dropout voltage of 95 mV typ. at full load current. The devices are
stable with ceramic and other low ESR output capacitors. This series
contains adjustable output voltage version with output voltage down
to 0.8 V. Internal protection features consist of built−in thermal
shutdown and output current limiting protection. User−programmable
Soft−Start and Power Good pins are available. The NCP59744 is
offered in DFN10 3x3 and QFN20 5x5 packages.
Features
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QFN20
CASE 485DB
DFN10
CASE 485C
PIN CONNECTIONS
IN
NC
NC
NC
OUT
5
4
3
2
1
20
19
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Current in Excess of 3.0 A
0.25% Typical Accuracy Over Line and Load
V
IN
Range: 0.8 V to 5.5 V
V
BIAS
Range: 2.2 V to 5.5 V
Output Voltage Range: 0.8 V to 3.6 V
Dropout Voltage: 95 mV at 3 A
Programmable Soft Start
Open Drain Power Good Output
Excellent Transient Response
Current Limit and Thermal Shutdown Protection
These are Pb−Free Devices
Telecom and Industrial Equipment Point of Load Regulation
FPGA, DSP and Logic Power Supplies
Switching Power Supply Post Regulation
Applications with Specific Start−up Time or Sequencing
Requirements
NCP59744
IN
IN
IN
PG
BIAS
6
7
8
9
10
11 12 13 14 15
GND
18
17
16
OUT
OUT
OUT
NC
FB
QFN20−5y5−0.65P
IN
IN
PG
BIAS
EN
1
2
3
4
5
10
9
EN
GND
NC
NC
SS
OUT
OUT
FB
SS
GND
Thermal
Pad
8
7
6
Applications
DFN10−3y3−0.5P
MARKING DIAGRAMS
1
NCP59744
AWLYYWWG
G
QFN20
A
WL, L
YY, Y
WW, W
G
1
NCP
59744
ALYWG
G
DFN10
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Figure 1. Typical Application Schematic
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
February, 2017 − Rev. 2
Publication Order Number:
NCP59744/D
NCP59744
0.45
mA
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Name
IN
EN
SS
BIAS
PG
DFN10
1, 2
5
7
4
3
QFN20
5−8
11
15
10
9
Unregulated input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the
regulator into shutdown mode. This pin must not be left floating.
Soft−Start pin. A capacitor connected on this pin to ground sets the start−up time. If
this pin is left floating, the regulator output soft−start ramp time is typically 200
ms.
Bias input voltage for error amplifier, reference, and internal control circuits.
Power−Good (PG) is an open−drain, active−high output that indicates the status of
V
OUT
. When V
OUT
exceeds the PG trip threshold, the PG pin goes into a
high−impedance state. When V
OUT
is below this threshold the pin is driven to a
low−impedance state. A pull−up resistor from 10 kW to 1 MW should be connected
from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
This pin is the feedback connection to the center tap of an external resistor divider
network that sets the output voltage. This pin must not be left floating.
Regulated output voltage. It is recommended that the output capacitor
≥
2.2
mF.
Description
FB
OUT
NC
GND
PAD/TAB
8
9, 10
N/A
6
16
1, 18−20
2−4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top−side plane.
12
Ground
Should be soldered to the ground plane for increased thermal performance
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2
NCP59744
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Input Voltage Range
Input Voltage Range
Enable Voltage Range
Power−Good Voltage Range
PG Sink Current
SS Pin Voltage Range
Feedback Pin Voltage Range
Output Voltage Range
Maximum Output Current
Output Short Circuit Duration
Continuous Total Power Dissipation
Maximum Junction Temperature
Storage Junction Temperature Range
P
D
T
JMAX
T
STG
Symbol
V
IN
V
BIAS
V
EN
V
PG
I
PG
V
SS
V
FB
V
OUT
I
OUT
Value
−0.3 to +6
−0.3 to +6
−0.3 to +6
−0.3 to +6
0 to +1.5
−0.3 to +6
−0.3 to +6
−0.3 to (V
IN
+ 0.3)
≤
6
Internally Limited
Indefinite
See Thermal Characteristics Table and Formula
+150
−55 to +150
°C
°C
Unit
V
V
V
V
mA
V
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latch−up Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, DFN10, 3x3, 0.5P package
Thermal Resistance, Junction−to−Ambient (Note 5)
Thermal Resistance, Junction−to−Case (bottom) (Note 7)
Thermal Characteristics, QFN20, 5x5, 0.65P package
Thermal Resistance, Junction−to−Ambient (Note 5)
Thermal Resistance, Junction−to−Board (Note 6)
Thermal Resistance, Junction−to−Case (bottom) (Note 7)
R
qJA
R
qJB
R
qJC
35.4
14.7
3.9
°C/W
°C/W
°C/W
R
qJA
R
qJC
41.5
6.6
°C/W
°C/W
Symbol
Value
Unit
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
− These data were generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
JEDEC51.7 guidelines. Top and Bottom layer 2 oz. copper, inner planes 1 oz. copper.
− DFN10: The exposed pad is connected to the PCB ground inner layer through a 3x2 thermal via array. Vias are 0.3 mm diameter, plated.
Each of top and bottom copper layers are assumed to have thermal conductivity representing 20% copper coverage.
− QFN20: The exposed pad is connected to the PCB ground inner layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated.
Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−board thermal resistance is simulated in an environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51−8.
7. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS
(Note 8)
Rating
Input Voltage
Bias Voltage
Junction Temperature
Symbol
V
IN
V
BIAS
T
J
Min
V
OUT
+ V
DO
2.2
−40
Max
5.5
5.5
125
Unit
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCP59744
(At V
EN
= 1.1 V, V
IN
= V
OUT
+ 0.3 V, C
BIAS
= C
IN
= 0.1
mF,
C
OUT
= 10
mF,
I
OUT
= 50 mA, V
BIAS
= 5.0 V, T
J
= −40°C to +125°C, unless
otherwise noted. Typical values are at T
J
= +25°C.)
Symbol
V
IN
V
BIAS
UVLO
V
REF
V
OUT
Parameter
Input voltage range
Bias pin voltage range
Undervoltage Lock−out
Internal reference (Adj.)
Output voltage range
Accuracy (Note 9)
V
BIAS
Rising Hysteresis
T
J
= +25°C
V
IN
= 5 V, I
OUT
= 1.5 A, V
BIAS
= 5 V
2.97 V
≤
V
BIAS
≤
5.25 V, V
OUT
+
1.62 V
≤
V
BIAS
50 mA
≤
I
OUT
≤
3.0 A
V
OUT(NOM)
+ 0.3
≤
V
IN
≤
5.5 V
0 mA
≤
I
OUT
≤
50 mA
50 mA
≤
I
OUT
≤
3.0 A
V
DO
V
IN
dropout voltage (Note 10)
V
BIAS
dropout voltage (Note 10)
I
CL
I
BIAS
I
SHDN
I
FB
PSRR
Current limit
Bias pin current
Shutdown supply current
Feedback pin current
Power−supply rejection
(V
IN
to V
OUT
)
I
OUT
= 3.0 A,
V
BIAS
– V
OUT(NOM)
≥
1.62 V
I
OUT
= 3.0 A, V
IN
= V
BIAS
V
OUT
= 80% x V
OUT(NOM)
0 mA
≤
I
OUT
≤
3.0 A
V
EN
≤
0.4 V
0 mA
≤
I
OUT
≤
3.0 A
1 kHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
1 MHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
Power−supply rejection
(V
BIAS
to V
OUT)
1 kHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
1 MHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
Noise
V
TRAN
t
STRT
I
SS
V
EN
,
HI
V
EN
,
LO
V
EN
,
HYS
V
EN
,
DG
I
EN
V
IT
V
HYS
V
PG
,
LO
I
PG
,
LKG
TSD
Output noise voltage
%V
OUT
droop during load
transient
Minimum startup time
Soft−start charging current
Enable input high level
Enable input low level
Enable pin hysteresis
Enable pin deglitch time
Enable pin current
PG trip threshold
PG trip hysteresis
PG output low voltage
PG leakage current
Thermal shutdown temperature
I
PG
= 1 mA (sinking), V
OUT
<
V
IT
V
PG
= 5.25 V, V
OUT
> V
IT
Shutdown, temperature increasing
Reset, temperature decreasing
0.03
+165
+140
V
EN
= 5 V
V
OUT
decreasing
86.5
100 Hz to 100 kHz, l
OUT
= 3 A
C
ss
= 1.0 nF
I
OUT
= 50 mA to 3.0 A at 1 A/ms,
C
OUT
= 10
mF,
V
OUT
= 3.3 V
I
OUT
= 1.5 A, C
SS
= open
V
SS
= 0.4 V
1.1
0
100
20
0.3
90
3
0.3
1
1
93.5
−250
3.8
Test Conditions
Min
V
OUT
+V
DO
2.2
1.2
−
0.796
V
REF
−1.0
±0.25
1.6
0.4
0.8
Typ
Max
5.5
5.5
1.9
−
0.804
3.6
+1.0
Unit
V
V
V
V
V
%
Table 5. ELECTRICAL CHARACTERISTICS − NCP59744MN1ADJTBG − DFN10
V
OUT
/V
IN
V
OUT
/I
OUT
Line regulation
Load regulation
0.0006
0.005
0.01
95
1.13
4.6
1.3
1
95
72
50
80
48
18 x V
OUT
±1.5
200
0.45
5.5
0.4
160
1.5
7
2
15
250
%/V
%/mA
%/A
mV
V
A
mA
mA
nA
dB
dB
mVrms
%V
OUT
ms
mA
V
V
mV
ms
mA
%V
OUT
%V
OUT
V
mA
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Adjustable devices tested at 0.8 V; external resistor tolerance is not taken into account.
10. Dropout is defined as the voltage from the input to V
OUT
when V
OUT
is 2% below nominal.
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NCP59744
(At V
EN
= 1.1 V, V
IN
= V
OUT
+ 0.3 V, C
BIAS
= C
IN
= 0.1
mF,
C
OUT
= 10
mF,
I
OUT
= 50 mA, V
BIAS
= 5.0 V, T
J
= −40°C to +125°C, unless
otherwise noted. Typical values are at T
J
= +25°C.)
Symbol
V
IN
V
BIAS
UVLO
V
REF
V
OUT
Parameter
Input voltage range
Bias pin voltage range
Undervoltage Lock−out
Internal reference (Adj.)
Output voltage range
Accuracy (Note 11)
V
BIAS
Rising Hysteresis
T
J
= +25°C
V
IN
= 5 V, I
OUT
= 1.5 A, V
BIAS
= 5 V
2.97 V
≤
V
BIAS
≤
5.25 V, V
OUT
+
1.62 V
≤
V
BIAS
50 mA
≤
I
OUT
≤
3.0 A
V
OUT(NOM)
+ 0.3
≤
V
IN
≤
5.5 V
0 mA
≤
I
OUT
≤
50 mA
50 mA
≤
I
OUT
≤
3.0 A
V
DO
V
IN
dropout voltage (Note 12)
V
BIAS
dropout voltage (Note 12)
I
CL
I
BIAS
I
SHDN
I
FB
PSRR
Current limit
Bias pin current
Shutdown supply current
Feedback pin current
Power−supply rejection
(V
IN
to V
OUT
)
I
OUT
= 3.0 A,
V
BIAS
– V
OUT(NOM)
≥
1.62 V
I
OUT
= 3.0 A, V
IN
= V
BIAS
V
OUT
= 80% x V
OUT(NOM)
0 mA
≤
I
OUT
≤
3.0 A
V
EN
≤
0.4 V
0 mA
≤
I
OUT
≤
3.0 A
1 kHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
1 MHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
Power−supply rejection
(V
BIAS
to V
OUT)
1 kHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
1 MHz, I
OUT
= 1.5 A,
V
IN
= 1.8 V, V
OUT
= 1.5 V
Noise
V
TRAN
t
STRT
I
SS
V
EN
,
HI
V
EN
,
LO
V
EN
,
HYS
V
EN
,
DG
I
EN
V
IT
V
HYS
V
PG
,
LO
I
PG
,
LKG
TSD
Output noise voltage
%V
OUT
droop during load
transient
Minimum startup time
Soft−start charging current
Enable input high level
Enable input low level
Enable pin hysteresis
Enable pin deglitch time
Enable pin current
PG trip threshold
PG trip hysteresis
PG output low voltage
PG leakage current
Thermal shutdown temperature
I
PG
= 1 mA (sinking), V
OUT
<
V
IT
V
PG
= 5.25 V, V
OUT
> V
IT
Shutdown, temperature increasing
Reset, temperature decreasing
0.03
+165
+140
V
EN
= 5 V
V
OUT
decreasing
86.5
100 Hz to 100 kHz, l
OUT
= 3 A
C
ss
= 1.0 nF
I
OUT
= 50 mA to 3.0 A at 1 A/ms,
C
OUT
= 10
mF,
V
OUT
= 3.3 V
I
OUT
= 1.5 A, C
SS
= open
V
SS
= 0.4 V
1.1
0
100
20
0.3
90
3
0.3
1
1
93.5
−250
3.8
Test Conditions
Min
V
OUT
+V
DO
2.2
1.2
−
0.796
V
REF
−1.0
±0.25
1.6
0.4
0.8
Typ
Max
5.5
5.5
1.9
−
0.804
3.6
+1.0
Unit
V
V
V
V
V
%
Table 6. ELECTRICAL CHARACTERISTICS − NCP59744MN2ADJTBG − QFN20
V
OUT
/V
IN
V
OUT
/I
OUT
Line regulation
Load regulation
0.0006
0.005
0.01
115
1.13
4.6
1.3
1
95
72
50
80
48
18 x V
OUT
±1.5
200
0.45
5.5
0.4
195
1.5
6
2
10
250
%/V
%/mA
%/A
mV
V
A
mA
mA
nA
dB
dB
mVrms
%V
OUT
ms
mA
V
V
mV
ms
mA
%V
OUT
%V
OUT
V
mA
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Adjustable devices tested at 0.8 V; external resistor tolerance is not taken into account.
12. Dropout is defined as the voltage from the input to V
OUT
when V
OUT
is 2% below nominal.
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