Any frequency between 1 MHz and 110 MHz accurate to 6 decimal
places
Operating temperature from -40°C to 85°C. Refer to
SiT2018
for
-40°C to 85°C option and
SiT2020
for -55°C to 125°C option
Excellent total frequency stability as low as ±20 ppm
Low power consumption of 3.6 mA typical
Fast startup time of 5 ms
LVCMOS/HCMOS compatible output
5-pin SOT23-5: 2.9mm x 2.8mm
Pb-free, RoHS and REACH compliant
For AEC-Q100 one- output clock generators, refer to
SiT2024
and
SiT2025
Industrial, medical, automotive, avionics and other high temper-
ature applications
Industrial sensors, PLC, motor servo, outdoor networking
equipment, medical video cam, asset tracking systems, etc.
Electrical Specifications
Table 1. Electrical Characteristics
[1, 2]
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-20
-25
-50
Operating Temperature Range
(ambient)
T_use
-20
-40
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_od
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
Typ.
–
–
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
3.8
3.6
3.4
–
–
2.6
1.4
0.6
–
1.0
1.3
1.0
–
Max.
110
+20
+25
+50
+70
+85
1.98
2.75
3.08
3.3
3.63
3.63
4.5
4.2
3.9
4.3
4.1
4.3
2.5
1.3
55
2.0
2.5
2.0
–
Unit
MHz
ppm
ppm
ppm
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
%
ns
ns
ns
Vdd
No load condition, f = 20 MHz, Vdd = 2.8V, 3.0V or 3.3V
No load condition, f = 20 MHz, Vdd = 2.5V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = Low, output in high Z state.
Vdd = 1.8V, OE = Low, output in high Z state.
Vdd = 2.8V to 3.3V, ST = Low, Output is Weakly Pulled Down
Vdd = 2.5V, ST = Low, Output is Weakly Pulled Down
Vdd = 1.8V, ST = Low, Output is Weakly Pulled Down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V or 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V or 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Condition
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Extended Commercial
Industrial
Supply Voltage and Current Consumption
Supply Voltage
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
SiTime Corporation
Rev. 1.0
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 16, 2014
SiT9201
Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Table 1. Electrical Characteristics
[1, 2]
(continued)
Parameters
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
Symbol
VIH
VIL
Z_in
Min.
70%
–
50
2
Startup Time
Enable/Disable Time
Resume Time
RMS Period Jitter
Peak-to-peak Period Jitter
RMS Phase Jitter (random)
T_start
T_oe
T_resume
T_jitt
T_pk
T_phj
–
–
–
–
–
–
–
–
–
Typ.
–
–
87
–
–
–
–
1.76
1.78
12
14
0.5
1.3
Max.
–
30%
150
–
5
130
5
Jitter
3
3
20
25
0.9
2
ps
ps
ps
ps
ps
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Unit
Vdd
Vdd
k
M
ms
ns
ms
Pin 3, OE or ST
Pin 3, OE or ST
Pin 3, OE logic high or logic low, or ST logic high
Pin 3, ST logic low
Measured from the time Vdd reaches 90% of final value
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * clock
periods
Measured from the time ST pin crosses 50% threshold
Condition
Input Characteristics
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25°C temperature.
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output
Enable
3
OE/ ST/NC
Standby
No Connect
4
5
VDD
OUT
Power
Output
Electrical ground
[3]
No connect
H
[4]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[4]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Any voltage between 0 and Vdd or Open
[4]
: Specified frequency
output. Pin 3 has no function.
Power supply voltage
[3]
Oscillator output
4
5
Functionality
Top View
OE/ST/NC NC
3
2
GND
1
VDD
OUT
Notes:
3. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
4. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven.
If pin 3 needs to be left floating, use the NC option.
Figure 1. Pin Assignments
Rev. 1.0
Page 2 of 12
www.sitime.com
SiT9201
Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
N
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the
IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[5]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[6]
Package
SOT23-5
JA
, 4 Layer Board
(°C/W)
421
JC
, Bottom
(°C/W)
175
Note:
6. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[7]
Max Operating Temperature (ambient)
70°C
85°C
Maximum Operating Junction Temperature
80°C
95°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.0
Page 3 of 12
www.sitime.com
SiT9201
Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
[8]
Test
Point
Vout
Vdd
Tr
5
4
0.1µF
Power
Supply
Tf
15 pF
(including probe
and fixture
capacitance)
1
2
3
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
Vdd
1k
Ω
OE/ST Function
Figure 2. Test Circuit
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
90% Vdd
Vdd
50% Vdd
Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[9]
ST Voltage
T_resume
CLK Output
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
u
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
50% Vdd
OE Voltage
T_oe
OE Voltage
Vdd
50% Vdd
T_oe
CLK Output
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
9. SiT9201 has “no runt” pulses and “no glitch” output during startup or resume.
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