DEMO MANUAL DC2512A
HSMC Adapter for DC718-
Compatible Demo Boards
DESCRIPTION
Demonstration circuit 2512A is a gasket adapter board that
allows DC718-compatible data converter eval boards to
interface with FPGA boards that have an HSMC connec-
tor, such as the SoCkit Cyclone 5 SoC development board
from Arrow Electronics.
SET TO 3.3V UNLESS OTHER
VOLTAGE IS SPECIFIED
Design files for this circuit board are available at
http://www.linear.com/demo/DC2512A
L,
LT, LTC, LTM, Linear Technology, the Linear logo and Linduino are registered trademarks
and QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
DC718-COMPATIBLE
ADC BOARD
MATED TO J1
DC2512A F01
Figure 1. Basic Connections
dc2512af
1
DEMO MANUAL DC2512A
QUICK START PROCEDURE
DC2512A was designed to mate to the Arrow SoCkit board.
DC2512A may work with other HSMC-compatible FPGA
boards, but the pin connections and voltages should be
verified.
Carefully mate the HSMC connector on the reverse side of
the DC2512A to the SoCkit board. Use high-quality, 5mm
spacers such as Harwin R30-6200514, and M3 × 12 or
4-40 × 1/2" pan-head screws.
Most FPGA loads intended for use with the DC2512A
require 3.3V I/O voltage. Unless the test script or other
experiment documentation indicates otherwise, set the
SoCkit’s I/O voltage to 3.3V by placing the JP2 jumper
on the SoCkit board in the 3.3V position (closest to the
edge of the board). Mate the ADC demo board to J1 on
DC2512A. Observe proper power-sequencing: the best
practice is to power up the SoCkit before applying power
to the ADC demo board.
A complete example of a typical evaluation setup is covered
in the blog, “Data Converter Evaluation with the Arrow /
Altera SoCkit FPGA board”:
http://www.linear.com/solutions/7704
EXTERNAL CONNECTIONS
Mapping of individual pins is shown in Table 1.
J1:
2x40, 0.1" (2.54mm) receptacle, compatible with ADC
demo boards that are used with the DC718 capture board.
Signals include conversion clock, up to 18 data lines, I
2
C
signals for identification, and 3.3V auxiliary power.
J2:
2x7 QuikEval™/Linduino
®
connector. Not used for
basic ADC evaluation. Allows the FPGA board to control
Table 1. Pin Mapping
DC2512A HEADER/PIN
DC2512A SIGNAL NAME
HSMC SIGNAL NAME
HSMC_CLK_IN0
HSMC_CLKIN_n1
HSMC_CLKIN_n2
J1, Pin 3
CCLK+
HSMC_CLKIN_p1
HSMC_CLKIN_p2
HSMC_CLK_OUT0
J3, Pin 29
J3, Pin 31
HSMC_CLKOUT_p1
HSMC_CLKOUT_n1
HSMC_CLKOUT_p2
HSMC_CLKOUT_n2
J2, Pin 4
J2, Pin 7
J2, Pin 6
J2, Pin 5
J1, Pin 1
J1, Pin 2
J1, Pin 37
SCK/SCL
MOSI/SDA
CS#
MISO
SCL
SDA
D0
HSMC_D[0]
HSMC_D[1]
HSMC_D[2]
HSMC_D[3]
HSMC_SCL
HSMC_SDA
HSMC_RX _p[0]
SoCkit FPGA PIN NO.
PIN_J14
PIN_AB27
PIN_G15
PIN_AA26
PIN_H15
PIN_AD29
PIN_E7
PIN_E6
PIN_A11
PIN_A10
PIN_C10
PIN_H13
PIN_C9
PIN_H12
PIN_AA28
PIN_AE29
PIN_G12
dc2512af
QuikEval-compatible demo boards for experiments or
application development.
J3, J4:
Test pads for additional HSMC signals.
12V, GND, 3.3V Turret Posts:
12V and 3.3V, supplied
through the HSMC connector. May be used to power
additional circuitry, refer to SoCkit documentation for
maximum current. Do NOT apply power to these points.
2
5
4
3
2
ECO
__
2
PRODUCTION
MARK T.
09-14-16
REV
REVISION HISTORY
DESCRIPTION
APPROVED
DATE
1
J1
12V
ASP-122952-01
ASP-122952-01
3V3AUX
12V
3V3AUX
D
P1B
P1C
HD2X16-079-SMT
GND
GND
SDA
D
168
166
GND
GND
HD2X13-079-SMT
GND
J3
J4
172
170
GND
GND
CCLK+
D15
D14
D13
D12
D11
D10
D9
D8
GND
SCHEMATIC DIAGRAM
D17
D16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
25
23
21
19
17
15
13
11
9
7
5
3
1
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
26
24
22
20
18
16
14
12
10
8
6
4
2
D5
D4
D3
D2
SCL
CCLK+
D18
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3V3AUX
GND
D7
D6
SAMTEC, BCS-120-L-D-TE
EDGE MOUNT SOCKET
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND
HD2X7-079-MOLEX
J2
D18
D17
D16
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
12V
CLKIN1N
CLKIN1P
12V
LVDS_RXN7
LVDS_RXP7
12V
LVDS_RXN6
LVDS_RXP6
12V
LVDS_RXN5
LVDS_RXP5
12V
LVDS_RXN4
LVDS_RXP4
12V
LVDS_RXN3
LVDS_RXP3
12V
LVDS_RXN2
LVDS_RXP2
12V
LVDS_RXN1
LVDS_RXP1
12V
LVDS_RXN0
LVDS_RXP0
12V
D3
D1
GND
C
D1
D0
V+
5V
49.9
49.9
49.9
49.9
AUX
LIN-SENSE
1
2
R1
0
3V3AUX
BANK 2
167
GND 165
GND
99
3V3 97
CLKOUT1N 95
CLKOUT1P 93
3V3 91
LVDS_TXN7 89
LVDS_TXP7 87
3V3 85
LVDS_TXN6 83
LVDS_TXP6 81
3V3 79
LVDS_TXN5 77
LVDS_TXP5 75
3V3 73
LVDS_TXN4 71
LVDS_TXP4 69
3V3 67
LVDS_TXN3 65
LVDS_TXP3 63
3V3 61
LVDS_TXN2 59
LVDS_TXP2 57
3V3 55
LVDS_TXN1 53
LVDS_TXP1 51
3V3 49
LVDS_TXN0 47
LVDS_TXP0 45
3V3 43
D2 41
D0
160
158
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
12V
CLKIN2N
CLKIN2P
12V
LVDS_RXN16
LVDS_RXP16
12V
LVDS_RXN15
LVDS_RXP15
12V
LVDS_RXN14
LVDS_RXP14
12V
LVDS_RXN13
LVDS_RXP13
12V
LVDS_RXN12
LVDS_RXP12
12V
LVDS_RXN11
LVDS_RXP11
12V
LVDS_RXN10
LVDS_RXP10
12V
LVDS_RXN9
LVDS_RXP9
12V
LVDS_RXN8
LVDS_RXP8
BANK 3
171
GND 169
GND
159
3V3 157
CLKOUT2N 155
CLKOUT2P 153
3V3 151
LVDS_TXN16 149
LVDS_TXP16 147
3V3 145
LVDS_TXN15 143
LVDS_TXP15 141
3V3 139
LVDS_TXN14 137
LVDS_TXP14 135
3V3 133
LVDS_TXN13 131
LVDS_TXP13 129
3V3 127
LVDS_TXN12 125
LVDS_TXP12 123
3V3 121
LVDS_TXN11 119
LVDS_TXP11 117
3V3 115
LVDS_TXN10 113
LVDS_TXP10 111
3V3 109
LVDS_TXN9 107
LVDS_TXP9 105
3V3 103
LVDS_TXN8 101
LVDS_TXP8
C
R2
R3
R4
SET LINDUINO TO +3.3V
6
CS 4
SCK/SCL 7
MOSI/SDA 5
MISO
10
EEVCC 9
EESDA 11
EESCL 12
EEGND 14
AUX
R5
GND
GND
GND
3V3AUX
R7
49.9
13
8
3
R6
5.49k
ASP-122952-01
B
P1A
B
E1
GND
12V
163
161
39
37
SDA
GND
GND
CLKOUT0
JTAG_TDO
JTAG_TCK
SDA
SCL
E2
3V3AUX
35
33
31
29
27
25
23
21
GND
XCVR_TXN1
XCVR_TXP1
XCVR_TXN2
XCVR_TXP2
XCVR_TXN3
XCVR_TXP3
XCVR_TXN4
XCVR_TXP4
XCVR_TXN5
XCVR_TXP5
GND
19
17
15
13
11
9
7
5
3
1
XCVR_TXN7
XCVR_TXP7
XCVR_TXN6
XCVR_TXP6
GND
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
XCVR_TXN0
XCVR_TXP0
E3
CUSTOMER NOTICE
A
APPROVALS
KIM T.
MARK T.
TECHNOLOGY
TITLE: SCHEMATIC
BANK 1
164
GND 162
GND
40
CLKIN0 38
JTAG_TDI
36
JTAG_TMS 34
SCL
32
XCVR_RXN0 30
XCVR_RXPO
28
XCVR_RXN1 26
XCVR_RXP1
24
XCVR_RXN2 22
XCVR_RXP2
20
XCVR_RXN3 18
XCVR_RXP3
16
XCVR_RXN4 14
XCVR_RXP4
12
XCVR_RXN5 10
XCVR_RXP5
8
XCVR_RXN6 6
XCVR_RXP6
4
XCVR_RXN7 2
XCVR_RXP7
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
A
HSMC ADAPTER FOR DC718-COMPATIBLE DEMO BOARDS
SIZE
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
N/A
SCALE = NONE
2
IC NO.
DATE:
DEMO CIRCUIT 2512A
Wednesday, September 14, 2016
1
REV.
2
SHEET
1
OF
1
5
4
DEMO MANUAL DC2512A
dc2512af
5
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