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570PBC000635DG

Description
OSC XO 35.3200MHZ CMOS SMD
CategoryPassive components    oscillator   
File Size562KB,36 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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570PBC000635DG Overview

OSC XO 35.3200MHZ CMOS SMD

570PBC000635DG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codecompliant
Oscillator typeCMOS
Si 5 7 0 / S i 5 7 1
10 MH
Z
Features
TO
1.4 G H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
Ordering Information:
SONET/SDH
xDSL
10 GbE LAN/WAN
ATE
High performance
instrumentation
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 31.
Pin Assignments:
See page 30.
(Top View)
SDA
7
NC
1
6
V
DD
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-
programmable to any output frequency from 10 to 945 MHz and select frequencies
to 1400 MHz with <1 ppb resolution. The device is programmed via an I
2
C serial
interface. Unlike traditional XO/VCXOs where a different crystal is required for
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL
clock synthesis IC to provide any-frequency operation. This IC-based approach
allows the crystal resonator to provide exceptional frequency stability and
reliability. In addition, DSPLL clock synthesis provides superior supply noise
rejection, simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems.
OE
2
5
CLK–
GND
3
8
SCL
4
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
7
OE
Fixed
Frequency
XO
10-1400 MHz
DSPLL Clock
Synthesis
V
C
1
6
V
DD
SDA
SCL
OE
2
5
CLK–
Si571 only
ADC
GND
3
8
SCL
4
CLK+
GND
V
C
Si571
Si570/Si571
Rev. 1.6 6/18
Copyright © 2018 by Silicon Laboratories
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Index Files: 2530  2549  2212  280  240  51  52  45  6  5 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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