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CY7C1327B
256K x 18 Synchronous-Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 256K by 18 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
•
•
•
•
•
•
— 5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
The CY7C1327B I/O pins can operate at either the 2.5V or the
3.3V level. The I/O pins are 3.3V tolerant when V
DDQ
=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1327B supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the four Byte Write
Select (BW
[1:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Functional Description
The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[17:0]
GW
BWE
BW
1
BW
0
MODE
(A
[1;0]
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
16
18
18
16
D DQ[15:8], DP[1] Q
BYTEWRITE
REGISTERS
D DQ[7:0], DP[0] Q
BYTEWRITE
REGISTERS
256KX18
MEMORY
ARRAY
CE
1
CE
2
CE
3
18
D
ENABLE CE
CE REGISTER
Q
18
D ENABLE DELAY Q
REGISTER
OE
ZZ
SLEEP
CONTROL
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ
[15:0]
DP
[1:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
Document #: 38-05140 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 6, 2001
CY7C1327B
Selection Guide
7C1327-166
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
3.5
420
10
7C1327-133
4.0
375
10
7C1327-100
5.5
325
10
Pin Configurations
100-Lead TQFP
OE
ADSC
BWS
1
BWS
0
ADSP
ADV
84
83
BWE
CE
1
CE
2
CE
3
V
DD
CLK
V
SS
GW
NC
NC
A6
A7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
NC
V
DD
NC
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
A
10
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
NC
V
DD
ZZ
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE0
CY7C1327B
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
A
17
BYTE1
DNU
DNU
DNU
DNU
A
11
A
12
A
13
A
14
MODE
A
5
V
SS
Document #: 38-05140 Rev. **
V
DD
A
15
A
16
A
4
A
3
A
2
A
1
A
0
Page 2 of 17
CY7C1327B
Pin Configurations
(continued)
119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DQP
b
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
V
ss
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
NC
5
A
A
A
V
SS
V
SS
V
SS
V
ss
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
V
SS
A
NC
6
A
CE
3
A
DQP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
ZZ
V
DDQ
Pin Definitions
Name
A
[17:0]
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the
2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW
[1:0]
and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
2
to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input-
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
Synchronous is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
I/O
Input-
Synchronous
BW
[1:0]
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
ADV
ADSP
Document #: 38-05140 Rev. **
Page 3 of 17
CY7C1327B
Pin Definitions
(continued)
Name
ADSC
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
is
captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
[1:0]
are placed
in a three-state condition.
Power Supply Power Supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground
Ground for the core of the device. Should be connected to ground of the system.
I/O Power
Power Supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Supply
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
Static
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal
pull-up.
No Connects.
is HIGH. The address presented to the address inputs (A
[17:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[17:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[1:0]
) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
[15:0]
and DP
[1:0]
inputs is written into
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[1:0]
signals. The CY7C1327B provides byte write capabil-
ity that is described in the Write Cycle Description table. As-
serting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
[1:0]
) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Page 4 of 17
I/O
Input-
Synchronous
ZZ
DQ
[15:0]
DP
[1:0]
V
DD
V
SS
V
DDQ
V
SSQ
MODE
NC
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz
device).
The CY7C1327B supports secondary cache in systems utiliz-
ing either a linear or interleaved burst sequence. The inter-
leaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[1:0]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
Document #: 38-05140 Rev. **
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