552BD000118DGR datasheet, PDF - EEWORLD Datasheet

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552BD000118DGR: DescriptionVCXO; DIFF/SE; DUAL FREQ; 10-141; CategoryPassive components; File Size477KB，15 Pages; ManufacturerSilicon Laboratories Inc

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552BD000118DGR Overview

VCXO; DIFF/SE; DUAL FREQ; 10-141

552BD000118DGR Parametric

Parameter Name	Attribute value
type	VCXO
Frequency - Output 1	74.175824MHz，74.25MHz
Frequency - Output 2	-
Frequency - Output 3	-
Frequency - Output 4	-
Function	enable/disable
output	LVDS
Voltage - Power	3.3V
frequency stability	±50ppm
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	108mA
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
high	0.071"（1.80mm）
Package/casing	6-SMD, no leads
Current - Power (disabled) (maximum)	75mA

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Si 5 5 2

EVISION

U A L

REQUENCY

OLTAGE

- C

ON TROLLED

R Y S TA L

SCILLATOR

(VCXO) 10 MH

Z TO

1 . 4 G H

Features

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz



Two selectable output frequencies



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than

SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH



xDSL



10 GbE LAN/WAN



Ordering Information:

Low-jitter clock generation



Optical modules



Clock and data recovery



See page 10.

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Pin Assignments:

See page 9.

(Top View)

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 1.2 6/18

Si552

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