SN74LS373, SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
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LOW
POWER
SCHOTTKY
MARKING
DIAGRAMS
SN74LS37xN
AWLYYWW
20
1
1
•
•
•
•
•
•
•
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects
PDIP–20
N SUFFIX
CASE 738
20
LS37x
AWLYYWW
1
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
–2.6
24
Unit
V
°C
mA
mA
20
1
SOIC–20
DW SUFFIX
CASE 751D
74LS37x
AWLYWW
1
SOEIAJ–20
M SUFFIX
CASE 967
x
A
WL
YY
WW
1
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2001
1
October, 2001 – Rev. 8
Publication Order Number:
SN74LS373/D
SN74LS373, SN74LS374
CONNECTION DIAGRAM DIP
(TOP VIEW)
SN74LS373
VCC O7
20
19
D7
18
D6
17
O6
16
O5
15
D5
14
D4
13
O4
12
LE
11
VCC O7
20
19
D7
18
SN74LS374
D6
17
O6
16
O5
15
D5
14
D4
13
O4
12
CP
11
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
D2
8
D3
9
O3
10
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In Line Package.
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
D2
8
D3
9
O3
10
GND
LOADING
(Note a)
PIN NAMES
D0 - D7
LE
CP
OE
O0 - O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
TRUTH TABLE
LS373
Dn
H
L
X
X
LE
H
H
L
X
OE
L
L
L
H
On
H
L
Q0
Z*
Dn
H
L
X
X
LS374
LE
OE
L
L
H
On
H
L
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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2
SN74LS373, SN74LS374
LOGIC DIAGRAMS
SN74LS373
3
4
7
8
13
14
17
18
V
CC
= PIN 20
GND = PIN 10
D0
D
LATCH
ENABLE
D1
Q
G
D
Q
G
D2
D
Q
G
D3
D
Q
G
D4
D
Q
G
D5
D
Q
G
D6
D
Q
G
D7
D
Q
G
= PIN NUMBERS
11
LE
OE
O0
2
5
1
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
SN74LS374
3
11
4
7
8
13
14
17
18
D0
CP D
Q Q
CP D
Q Q
D1
CP D
Q Q
D2
CP D
Q Q
D3
CP D
Q Q
D4
CP D
Q Q
D5
CP D
Q Q
D6
CP D
Q Q
D7
CP
OE
1
2
O0
5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.4
–0.65
3.1
0.25
VOL
IOZH
IOZL
IIH
IIL
IOS
Output LOW Voltage
0.35
Output Off Current HIGH
Output Off Current LOW
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 1)
–30
0.5
20
–20
20
0.1
–0.4
–130
V
µA
µA
µA
mA
mA
mA
0.4
Min
2.0
0.8
–1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = –18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 12 mA
IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
ICC
Power Supply Current
40
mA
1. Not more than one output should be shorted at a time, nor for more than 1 second.
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3
SN74LS373, SN74LS374
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
LS373
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Maximum Clock Frequency
Propagation Delay,
Data to Output
Clock or Enable
to Output
Output Enable Time
Output Disable Time
12
12
20
18
15
25
12
15
18
18
30
30
28
36
20
25
15
19
20
21
12
15
28
28
28
28
20
25
Min
Typ
Max
Min
35
LS374
Typ
50
Max
Unit
MHz
ns
ns
ns
ns
CL = 5.0 pF
CL = 45 pF
pF,
RL = 667
Ω
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
LS373
Symbol
tW
ts
th
Clock Pulse Width
Setup Time
Hold Time
Parameter
Min
15
5.0
20
Max
Min
15
20
0
LS374
Max
Unit
ns
ns
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373
AC WAVEFORMS
tW
LE
1.3 V
ts
Dn
tPLH
OUTPUT
tPHL
th
tW
Figure 1.
OE
tPZL
VOUT
1.3 V
0.5 V
1.3 V
1.3 V
tPLZ
1.3 V
VOL
OE
tPZH
VOUT
1.3 V
1.3 V
tPHZ
1.3 V
VOH
1.3 V
0.5 V
Figure 2.
Figure 3.
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