SRK2001A
Adaptive synchronous rectification controller for LLC resonant
converter
Datasheet
-
production data
Description
The SRK2001A controller implements a control
scheme specific for secondary side synchronous
rectification in LLC resonant converters that use a
transformer with center tap secondary winding for
full wave rectification.
It provides two high current gate drive outputs,
each capable of directly driving N-channel power
MOSFETs. Each gate driver is controlled
separately and an interlock logic circuit prevents
the two synchronous rectifier MOSFETs from
conducting simultaneously.
The driver high-level voltage is clamped to 11 V in
order to avoid providing excessive gate charge to
SR MOSFETs, in case the device is supplied at
higher VCC voltages.
The control scheme in this IC provides for each
synchronous rectifier being switched on as the
corresponding half-winding starts conducting and
switched off as its current goes to zero.
The turn-on logic with adaptive masking time (up
to 10% of clock cycle) and innovative adaptive
turn-off logic allow maximizing the conduction
time of the SR MOSFETs, eliminating the need of
the parasitic inductance compensation circuit.
The low consumption mode of the device allows
to meet the most stringent requirement for
converter power consumption in light-load and no
load conditions.
A noticeable feature is the very low external
component count required.
Table 1. Device summary
Order code
SRK2001A
SRK2001ATR
Package
SSOP10
Packing
Tube
Tape and reel
Features
Secondary side synchronous rectification
controller optimized for LLC resonant converter
Dual gate driver for N-channel MOSFETs
Adaptive turn-off logic
Turn-on logic with adaptive masking time
Auto-compensation of parasitic inductance
Low consumption mode: 50 μA quiescent
current
V
CC
operating voltage range 4.5 V to 32 V
High voltage drain-to-source Kelvin sensing for
each SR MOSFET
Operating frequency up to 500 kHz
Programmable exit load levels from burst-
mode
SSOP10 package
Applications
AC-DC adapters
All-in-one PC
High-end flat panel TV
80+/85+ compliant ATX SMPS
90+/92+ compliant SERVER SMPS
Industrial SMPS
September 2018
This is information on a product in full production.
DS11726 Rev 2
1/20
www.st.com
Contents
SRK2001A
Contents
1
2
3
4
5
6
7
Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.1
7.2
7.3
7.4
7.5
7.6
Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Adaptive turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ZCD_OFF comparator turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EN and PROG pins: function and usage . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.6.1
7.6.2
7.6.3
EN pin remote on-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst-mode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low consumption state exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.7
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1
SSOP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
DS11726 Rev 2
Rev 2
Block diagrams
1
Block diagrams
Figure 1. Internal block diagram
Figure 2. Typical system block diagram
DS11726 Rev 2
3/20
20
Pin connections and functions
SRK2001A
2
Pin connections and functions
Figure 3. Pin connections (top view)
Table 2. Pin functions
No.
1
Name
VCC
Function
Supply voltage of the device. A bypass capacitor to GND, located as close to IC's pins
as possible, helps to get a clean supply voltage for the internal control circuitry and
acts as an effective energy buffer for the pulsed gate drive currents.
Return of the device bias current and return of the gate drive currents. Route this pin
to the common point where the source terminals of both synchronous rectifier
MOSFETs are connected.
Gate driver output for section 1 (2). Each totem pole output stage is able to drive
power MOSFETs with high peak current levels. To avoid excessive gate voltages in
case the device is supplied with a high V
CC
, the high-level voltage of these pins is
clamped to about 11 V. The pin has to be connected directly to the SR MOSFET gate
terminal.
2
GND
3
(8)
GD1
(GD2)
Source voltage sensing for section 1 (2): it is the reference voltage of the
SVS1
corresponding drain sensing signal on the DVS1,2 pin. These pins have to be
4
(SVS2)
connected directly to the respective source terminals of the corresponding
(7)
synchronous rectifier MOSFET.
Drain voltage sensing for section 1 (2). These pins have to be connected to the
5
DVS1
respective drain terminals of the corresponding synchronous rectifier MOSFET using
(6) (DVS2)
a series resistor of 100
.
Programming pin for conduction duty-cycle at burst-mode exiting. A resistor
connected from this pin to GND, supplied by an internal precise current source, sets a
voltage V
PROG
; depending on this voltage level, during the start-up phase, the user
PROG can choose, according to the application requirements, the proper burst-mode exiting
conduction duty-cycle among the ones contained in an internal lookup table which
values are reported in
Table 6
(the values are predefined inside the table). For the
proper choice of the resistor value see
Table 5.
Enable pin function with internal pull-up (remote ON/OFF): during the run mode, when
the pin voltage is sensed below the internal threshold V
EN_OFF
, the controller stops
operating and enters a low consumption state; it resumes the operation if the pin
voltage surpasses the threshold V
EN_ON
.
9
10
EN
4/20
DS11726 Rev 2
Rev 2
Absolute maximum ratings
3
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
V
CC
I
CCZ
V
PROG
V
EN
DVS1,2
SVS1,2
Pin
1
1
10
9
5, 6
4, 7
DC supply voltage
Internal Zener maximum current (V
CC
= V
CCZ
)
PROG pin voltage rating
EN pin voltage rating
Drain sense voltage referred to source SVS1,2
Source sense voltage referred to GND
Parameter
Value
-0.3 to V
CCZ
25
-0.3 to 3.3
-0.3 to 3.3
-3 to 90
-3 to 3
Unit
V
mA
V
V
V
V
4
Thermal data
Table 4. Thermal data
Symbol
R
th j-amb
P
tot
T
j
T
stg
Parameter
Max. thermal resistance, junction to ambient
(1)
Value
130
10
0.75
-40 to 150
-55 to 150
Unit
°C/W
°C/W
W
°C
°C
R
th j-case
Max. thermal resistance, junction to case top
(1)
Power dissipation at T
amb
= 50 °C
Junction temperature operating range
Storage temperature
1. With the pin 2 soldered to a dissipating copper area of 25 mm2, 35 μm thickness (PCB material FR4
1.6 mm thickness).
DS11726 Rev 2
5/20
20
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