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535EB106M250DGR

Description
SINGLE FREQUENCY XO, OE PIN 2 (O
CategoryPassive components   
File Size600KB,12 Pages
ManufacturerSilicon Laboratories Inc
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535EB106M250DGR Overview

SINGLE FREQUENCY XO, OE PIN 2 (O

535EB106M250DGR Parametric

Parameter NameAttribute value
typeXO (Standard)
frequency106.25MHz
Functionenable/disable
outputLVPECL
Voltage - Power2.5V
frequency stability±20ppm
Absolute pulling range (APR)-
Operating temperature-40°C ~ 85°C
Current - Power (maximum)121mA
grade-
Installation typesurface mount
Package/casing6-SMD, no leads
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)0.071"(1.80mm)
Current - Power (disabled) (maximum)75mA
S i 5 3 5 / 5 36
R
EVISION
D
U
L T R A
L
O W
J
ITTER
C
RYSTAL
O
SCILLATOR
(XO)
Features
Available with select frequencies from
Available with LVPECL and
100 MHz to 312.5 MHz
LVDS outputs
3
rd
generation DSPLL
®
with superior
3.3 and 2.5 V supply options
Industry-standard 5 x 7 mm
jitter performance and high-power
package and pinout
supply noise rejection
Pb-free/RoHS-compliant
3x better frequency stability than
SAW-based oscillators
Si5602
Applications
10/40/100G data centers
10G Ethernet switches/routers
Fibre channel/SAS/storage
Ordering Information:
Enterprise servers
Networking
Telecommunications
See page 7.
Description
The Si535/536 XO utilizes Silicon Labs’ advanced DSPLL
®
circuitry to
provide an ultra low jitter clock at high-speed differential frequencies. Unlike a
traditional XO, where a different crystal is required for each output frequency,
the Si535/536 uses one fixed crystal to provide a wide range of output
frequencies. This IC based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low jitter clocks in noisy environments typically found in
communication systems. The Si535/536 IC based XO is factory programmed
at time of shipment, thereby eliminating long lead times associated with
custom oscillators.
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si535
Functional Block Diagram
V
DD
CLK– CLK+
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si536
Fixed
Frequency
XO
100–312.5 MHz
DSPLL
®
Clock Synthesis
OE
GND
Rev. 1.3 6/18
Copyright © 2018 by Silicon Laboratories
Si535/536
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