LQ
C
APACITANCE
TO
D
IGITAL
C
ONVERTER
QT300
Capacitance to Digital Converter (CDC) IC
Direct-to-digital conversion, 16 bits
Log response: Wide dynamic range
Outputs raw data to a host device
Single wire UART interface
Master or Slave mode SPI interface
Programmable clock speed
Turns objects into intrinsic touch sensors
One external sample capacitor to control gain
Multiple QT300’s possible on one SPI bus
Vss
4
DRDY
SCK
SNS1
1
8
Vdd
SDO
REQ / 1W
SNS2
QT300
2
3
7
6
5
The QT300 charge-transfer (“QT’”) IC is a self-contained Capacitance-to-
Digital-Converter (CDC) capable of detecting femotofarad level changes in
capacitance. While designed primarily for instrumentation applications, it can be used
also for touch control applications where signal processing is best handled by a host
MCU.
Primary applications include fluid level sensors, distance sensors, transducer
‘amplifiers’ for pressure and humidity sensing functions, material detectors, and other
uses requiring quantified capacitance data.
APPLICATIONS
Fluid level sensors
Prox sensors
Moisture detection
Position sensing
Transducer driver
Material sensors
Unlike other Quantum products, the QT300 does not process its acquired data. Its only result is raw, unprocessed binary
data which can be transmitted to a host via either a bidirectional SPI interface or a simple polled single wire UART type
interface. This allows the designer to treat the device as a capacitance-to-digital-converter (CDC) for measurement
applications. It is ideal for situations where there are unique signal processing requirements.
The device requires only a single sampling capacitor to function. The value of this capacitor controls the gain of the sensor,
and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components
are required.
The device operates on demand, and can be synchronized to allow several QT300’s to operate near each other without
cross-interference.
T
A
0 C to +70 C
-40
0
C to +85
0
C
0
0
AVAILABLE OPTIONS
SOIC
-
QT300-IS
8-PIN DIP
QT300-D
-
LQ
Copyright © 2002 QRG Ltd
QT300 R1.01 21/09/03
Table 1-1 SPI Mode Pin Description
Pin
Name
Function
1
2
3
4
5
6
7
8
/DRDY
SCK
SNS1
VSS
SNS2
/REQ
SDO
VDD
Data Ready
Serial data clock
Sense 1 line
Negative supply (ground)
Sense 2 line
Request input
Serial data out
Positive supply
QT 300
DRDY
SCK
Host Micro
REQ
SDI
Vdd
100nF
8
Vcc
1
DRDY
SCK
REQ
SDO
GND
4
SNS 1
SNS 2
3
5
SENSOR
CS
2
6
7
Table 1-2 1W UART Mode Pin Description
Pin
Name
Function
1
2
3
4
5
6
7
8
-
-
SNS1
VSS
SNS2
1W
-
VDD
Connect to Vdd or Vss
Connect to Vdd or Vss
Sense 1 line
Negative supply (ground)
Sense 2 line
1W UART Line
Connect to Vdd or Vss
Positive supply
Figure 1-1 Basic QT300 Circuit in SPI mode.
QT300
8
Vdd
SNS1
3
Electrode
1
2
Host Micro
7
(1W UART)
Rx
6
1W
SNS2
5
Table 1-3 Alternate Cloning Pin Functions
Pin
Name
Function
2
6
7
SCK
SDI
SDO
Serial clone data clock
Serial clone data in
Serial clone data out
Vss
4
Figure 1-2 Basic QT300 Circuit in UART mode.
1.2 CS / CX Dependency
The value returned is a direct function of Cs, the fixed sample
capacitor and Cx, the unknown or variable capacitance.
These two values influence device sensitivity and response
time, making them very important parameters.
Sensitivity is also a function of electrode size, shape,
orientation, the composition and aspect of the object being
sensed, the thickness and composition of any dielectric
overlaying the electrode, and the degree of mutual coupling
between the electrode and the object being sensed.
The response follows a logarithmic curve (Figures 7-4, 7-5,
Page 10); each doubling of Cs increases the signal level and
differential sensitivity by a factor of 2. Likewise, doubling Cx
reduces the signal level and differential sensitivity by a factor
of 2.
1 - OVERVIEW
The QT300 is a digital burst mode charge-transfer (QT)
capacitance-to-digital converter (CDC) designed for
applications requiring raw signal information such as fluid
level sensing and distance gauging; it outputs raw digital
signal data over a serial interface. The output data is in a
16-bit format; signal levels depend on load (Cx) and the
sampling capacitor value (Cs).
1.1 Basic Operation
The QT300 does no internal signal processing; data is simply
returned via one of two serial port types.
There are two basic types of serial interface: 4-wire SPI and
a simple single wire (‘1W’) UART. The SPI interface allows
multiple devices to be connected on one SPI bus, while
the1W UART requires that the controller have one dedicated
pin for each QT300. There are two types of SPI mode,
master and slave.
The type of serial port and its mode can be selected via the
cloning process using a QTM300CA programming adapter.
The QT300 operates only on request from a host device.
After initiation via a trigger signal, the QT300 generates an
acquisition burst and sends the resulting raw signal data
back via one of the serial modes.
2 - Timing
Figure 2-1 shows the basic QT300 acquisition timing
parameters. The basic timing parameters are:
Tbd
Tacq
Tbs
Burst duration
Acquire response time
Burst Spacing
(2.1)
(2.2)
(2.3)
2.1 Tbd - Burst duration
The burst duration depends on the values of Cs and Cx and
to a lesser extent, Vdd. The burst is composed of
charge-transfer cycles operating at about 240kHz.
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QT300 R1.01 21/09/03
The length of this burst is an important
parameter as it is directly related to the signal
value. The burst duration also affects the
response time of the sensor; the larger Cs is, the
longer the burst, the slower the possible
acquisition rate.
2.2 Tacq - Acquire Response Time
The time from the /REQ or 1W line going low
until the completion of data transmission is
Tacq. Tacq depends on the acquisition burst
length as well as the serial transmission time.
SPI Mode:
In SPI mode Tacq depends in part on
the serial clock speed and the space between
the returned high and low bytes. In SPI slave
mode the clock speed and the inter-byte spacing
time Tbdly is determine by the host. In SPI
Master mode these timings are set by Setup
parameters SCD and MLS.
1W mode:
Tacq depends in part on the Baud
rate as well as the inter-byte spacing. The Baud
rate is auto-set by the trigger pulse width; the
inter-byte spacing is set by the MLS parameter.
See Section 4.
2.3 Tbs - Burst Spacing
Burst spacing is the time from the start of one
acquisition burst to the start of the next burst. It
depends on the host’s trigger rate on the /REQ or 1W pin.
The QT300 only acquires when the host requests it.
While waiting for a new request the part is in a low power
mode.
Figure 2-1 Signal Acquisition - Slave SPI Mode
In master mode, /DRDY goes high between bytes for the
period determined by Setup parameter MLS; this is a multiple
of 6µs.
When not communicating, all SPI lines float to allow multiple
chips to connect over the same SPI lines. A pullup or
pulldown resistor is required on SCK depending on the
selected clock phase, determined by Setups. A pullup
resistor is required on /DRDY. /REQ may require a pullup if
the host ever allows this line to float.
3 - SPI Port
3.1 SPI Specifications
The QT300 can operate in master or slave mode, and thus is
compatible with virtually all SPI-capable microcontrollers. The
SPI interface has the following specifications:
Max clock rate, Fckm
Max clock rate, Fcks
Data length
Inter-byte delay
Clock idle logic level
Clock edge
Data sequence
40KHz (master mode)
40KHz (slave mode)
2 bytes (16 bits total)
≥8µs
(master mode)*
≥12µs
(slave mode)
Low or High*
Data out on rising or falling edge*
High byte first, MSB first
*Determined by Setups
The host can clock the SPI at any rate up to and including
the maximum. The maximum clock rate of the part in Master
mode is determined in Setups via cloning.
3.3 SPI Bus Sharing
All SPI float transfers making it possible to have several
QT300 devices (or other unrelated devices) share the SPI
control signals (Figure 3-1).
Each part needs an individual /REQ line, but /DRDY, SCK
and SDO can be connected together.
3.4 SPI Slave Mode
Refer to Figure 7-1 and Table 7-1, page 8.
In SPI Slave mode, /DRDY is used to let the host know when
data is ready for collection in response to a request so that
the host can clock over the data.
SPI Slave mode uses 4 signals:
/REQ
- Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
/REQ should return high before the end of the burst.
If
/REQ is still low at the end of the burst the part will go into
Setup mode. The minimum duration of /REQ is 30µs.
3.2 Protocol Overview
The QT300 only transmits data on request, after an
acquisition burst. The host requests an acquire by setting the
/REQ line low for at least 30µs; the device then acquires.
When finished, the DRDY line is pulled low by the QT300 to
indicate it is ready to send data. (Figure 2-1). The transfer is
done as two bytes, with the highest byte transferred first.
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QT300 R1.01 21/09/03
Figure 3-1 Multiple QT300's on the same SPI port
A typical
SPI slave mode
communication sequence is:
1) Host pulses /REQ low for
≥30µs
to initiate an acquire.
2) QT300 acquires a signal in response to /REQ.
Vdd
100nF
QT 300
DRDY
Host Micro
SCK
1
2
6
REQ2
REQ1
REQ3
8
Vcc
DRDY
SCK
REQ
SDO
GND
4
Vdd
3) QT300 pulls /DRDY low when ready to send data back.
4) Host detects /DRDY is low.
3
5
SENSOR
CS
SNS 1
SNS 2
5) Host clocks out the high byte of data from the QT300.
6) Host waits for
≥12µs.
7) Host clocks out the low byte of data from the QT300.
8) QT300 releases /DRDY to float high.
SDI
7
100nF
QT 300
8
Vcc
1
DRDY
2
6
7
SCK
REQ
SDO
GND
4
Vdd
SNS 1
SNS 2
3
5
SENSOR
CS
3.5 SPI Master Mode
Refer to Figure 7-2 and Table 7-2, page 8.
In master SPI mode the QT300 generates the clock signal
after an acquire initiated from the host via the /REQ line. The
clock speed and the spacing between the two bytes is set via
the Setup process (Section 6).
100nF
QT 300
8
Vcc
1
DRDY
2
6
7
SCK
REQ
SDO
GND
4
SNS 1
SNS 2
3
5
SENSOR
CS
SCD
setup parameter determines the master-mode clock
rate. The default value is 55 (resulting in a 2.55KHz rate).
The relationship is:
Fscd = 1200/(30+ (SCD x 8)) in Khz
Where SCD = 0..255
MLS
setup parameter determines the spacing between the
two return bytes; this can be important to allow a slow host
device to recover from receiving the first byte to prevent an
overrun. The default value is 148 (resulting in a 500µs gap).
The relationship is:
Tmls (in
µs)
= (10 + MLS x 4) / 1.2
Where MLS = 0..255 (from user setup MLS)
Master SPI mode requires at least 3 signals to operate:
/REQ
- Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
/REQ must return high before the end of the burst.
If
/REQ is still low at the end of the burst the part goes into
Setup mode. The minimum duration of /REQ is 30µs.
SDO
- Serial Data Output; Idle low output-only. This is the
data output to the host during an SPI transfer. When not in
use, this pin floats. This pin should be connected to the
SDI input pin of the host device.
SCK
- SPI clock; Idle high or idle low, output-only. The idle
state is determined in Setups by the serial mode (SM)
parameter.
If SM is set for idle-low SCK:
Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
If SM is set for idle-high SCK:
Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-2.
/DRDY
- Data Ready (Optional); active low output only. This
indicates to the host that the device is ready to send data
SDO
- Serial Data Output; Output-only. This is the data
output to the host during an SPI transfer. When not in use,
this pin floats. This pin should be connected to the SDI
input pin of the host device.
SCK
- SPI clock; Idle high or idle low; input-only SPI clock
from the host. The idle state is determined in Setups by
the serial mode (SM) parameter.
If SM is set for idle-low SCK:
Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
If SM is set for idle-high SCK:
Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-1.
/DRDY
- Data Ready; active low output only. This indicates to
the host that the device is ready to send data back to the
host. During idle times this pin floats and therefore must
be connected to a pullup resistor. The host must wait until
/DRDY goes low before starting an SPI transfer.
Between the high and low byte clockings, the host should
observe a delay of
≥12µs.
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QT300 R1.01 21/09/03
4 Single-Wire (1W) UART
Interface
The single wire ('1W') UART option allows all
communications to take place over a single
bidirectional line with a 10K pullup resistor. The host
device triggers the QT300 to acquire by means of a
pulse sent to the QT300 over the wire. The Baud rate
is established by the width of this pulse; the pulse
width establishes the bit rate of the UART
transmission to follow. The QT300 then acquires, and
responds by sending two bytes of data back over the
1W line with a delay between the bytes as determined
by parameter MLS.
1W operation permits a device to be controlled from a
single pin on a host controller, using either a hardware
or software UART. Several QT300’s can coexist on a
single host pin, provided there is some logic steering.
This mode is set via the cloning process using
parameter SM (see Section 6).
4.1 1W UART Specifications
The QT300 operates in 1W UART mode with the
following specifications:
Baud rate range
Data length
Stop bit
Parity
Idle state
4,800 to 9,600 bits/sec
2 bytes (16 bits total)
1 (each byte)
None
High
The 1W line must have a pullup resistor on it (i.e.
10K), or 1W communications will not function.
4.2 UART 1W Protocol
The QT300 acquires and transmits only on request.
The sequence is:
Figure 4-1 UART and Trigger Pulse Signal.
back to the host. During idle times this pin floats and
therefore must be connected to a pullup resistor.
The DRDY line can be used as a Slave Select line (SS).
The host does not need this line to operate in many cases.
DRDY can be used to 'frame' byte transmissions.
Between bytes /DRDY will go high for a period determined
by the MLS setup parameter; the minimum period is 8.3µs.
A typical Master mode SPI sequence is:
1) Host pulses /REQ low for
≥30µs.
2) QT300 acquires a signal in response to /REQ.
3) QT300 pulls /DRDY low when ready to send data.
4) Host detects /DRDY low and prepares to receive data.
5) QT300 clocks out first byte of data (MSB).
6) QT300 sets /DRDY high for a duration determined by
Setup parameter MLS.
7) QT300 pulls /DRDY low.
8) QT300 clocks out the low byte (LSB).
9) QT300 releases /DRDY to float high.
1) The host generates a pulse on the 1W pin; the
pulse width must match the Baud rate (bit width)
of the expected return Baud rate from the QT300.
This pulse actually sets the Baud rate each time,
and so it can vary from one acquire to another. See
Section 4.3 and Figure 4-1.
2) The 1W pulse width is measured by the QT300 to
determine the Baud rate.
3) The host floats 1W high.
4) The QT300 acquires the signal to completion.
5) QT300 returns data in the following UART format:
start bit (low)
8 bits, high byte
stop bit (high)
delay (determined by MLS setup)
start bit (low)
8 bits, low byte
stop bit (high)
6) The QT300 floats the 1W line and enters idle mode.
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QT300 R1.01 21/09/03
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