EEWORLDEEWORLDEEWORLD

Part Number

Search

550AD166M629DG

Description
VCXO; DIFF/SE; SINGLE FREQ; 10-1
CategoryPassive components   
File Size458KB,15 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

550AD166M629DG Online Shopping

Suppliers Part Number Price MOQ In stock  
550AD166M629DG - - View Buy Now

550AD166M629DG Overview

VCXO; DIFF/SE; SINGLE FREQ; 10-1

550AD166M629DG Parametric

Parameter NameAttribute value
typeVCXO
frequency166.629MHz
Functionenable/disable
outputLVPECL
Voltage - Power3.3V
frequency stability±50ppm
Absolute pulling range (APR)±80ppm
Operating temperature-40°C ~ 85°C
Current - Power (maximum)130mA
grade-
Installation typesurface mount
Package/casing6-SMD, no leads
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)0.071"(1.80mm)
Current - Power (disabled) (maximum)75mA
Si550
R
EVISION
D
V
O L TAG E
- C
ONTR OLLED
C
RYSTAL
O
S C I L L A T O R
(VCXO)
10 MH
Z TO
1 . 4 G H
Z
Features
Available with any frequency from
10 to 945 MHz and select
frequencies to 1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance (0.5 ps)
3x better temperature stability than
SAW-based oscillators
Excellent PSRR performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 10.
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 9.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si550 IC-based VCXO is factory-configurable
for a wide variety of user specifications, including frequency, supply voltage,
output format, tuning slope, and temperature stability. Specific configurations
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
Fixed
Frequency
XO
Any-Frequency
10 MHz–1.4 GHz
DSPLL
®
Clock Synthesis
CLK+
CLK–
Vc
ADC
OE
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si550
CCS installation crashed. . . . .
I cannot install Ware and Grace from the App Center. It’s been three days, and every time I try to install it, an error occurs halfway through. The error is always the same (PS: all antivirus and fire...
数码小叶 Microcontroller MCU
Problems with level conversion between FPGA and SJA1000 using SN74ALVC164245
FPGA and SJA1000 use SN74ALVC164245 for level conversion. AD0-AD7 of SJA1000 is connected to 1B1-1B8 of SN74ALVC164245, and 1DIR controls the direction. ALE, CS, WR, RD, and MODE of SJA1000 are connec...
shen19891209 FPGA/CPLD
ADC/DAC Special Study Part 2 - Principles
Chapter 2 Principles of ADC and DAC 1. Conversion Principle Digital quantity is represented by combining codes according to digits. For weighted codes, each code has a certain bit weight. In order to ...
七月七日晴 Analogue and Mixed Signal
Make a suggestion
I hope EEWORLD will set up a group and add all the members who bought Friendly Arm to the group. If you have any questions, you can communicate with each other. At the same time, Friendly Arm will pro...
jxb01033016 Embedded System
FPGA Serial Communication
FPGA (EP1C3T144) serial communication I send any data received 00, I changed the device settings, set a configuration device EPCS1 on the FPGA, and set the unused input pin to tri-state, the result is...
liujianhui Embedded System
Anyone got time to help me look at this?
/************************************************ Program function: MCU controls the buzzer to play the song "Wish you peace" ---------------------------------------------- Dip switch setting: turn th...
shyatupc Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2393  2593  1688  287  2530  49  53  34  6  51 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号