MTA9ASF51272AZ-2G1B1 datasheet, PDF

Datasheet> All Categories > storage> MTA9ASF51272AZ-2G1B1

MTA9ASF51272AZ-2G1B1: DescriptionIC SDRAM DDR4 4GB 512MX72 EUDIMM; Categorystorage; File Size391KB，19 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric Compare View All

MTA9ASF51272AZ-2G1B1 Overview

IC SDRAM DDR4 4GB 512MX72 EUDIMM

MTA9ASF51272AZ-2G1B1 Parametric

Parameter Name	Attribute value
memory type	DDR4 SDRAM
storage	4GB
speed	2133MT/s
Package/casing	288-UDIMM

Preview

Download Datasheet

View All

4GB (x72, ECC, SR) 288-Pin DDR4 UDIMM

Features

DDR4 SDRAM UDIMM

MTA9ASF51272AZ – 4GB

Features

• DDR4 functionality and operations supported as de-

fined in the component data sheet

• 288-pin, unbuffered dual in-line memory module

(UDIMM)

• Fast data transfer rates: PC4-2600, PC4-2400, and

PC4-2133

• 4GB (512 Meg x 72)

• V

= 1.20V (NOM)

• V

= 2.5V (NOM)

• V

DDSPD

= 2.5V (NOM)

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Low-power auto self refresh (LPASR)

• Data bus inversion (DBI) for data bus

• On-die V

REFDQ

generation and calibration

• Single-rank

• On-board I

C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• 16 internal banks; 4 groups of 4 banks each

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Table 1: Key Timing Parameters

Data Rate (MT/s)

Industry

Speed Nomen-

Grade clature

-2G6

-2G4

-2G3

-2G1

PC4-2666

PC4-2400

PC4-2133

CL =

20,

CL =

2666

–

Figure 1: 288-Pin UDIMM (MO-309, R/C D1)

Module height: 31.25mm (1.23in)

Options

• Operating temperature

– Commercial

(0°C

≤

OPER

≤

95°C)

• Package

– 288-pin DIMM (halogen-free)

• Frequency/CAS latency

– 0.75ns @ CL = 19 (DDR4-2666)

– 0.83ns @ CL = 17 (DDR4-2400)

– 0.93ns @ CL = 15 (DDR4-2133)

Marking

None

-2G6

-2G3

-2G1

CL =

2666

2400

–

CL =

2400

–

CL =

2133

2400

2133

CL =

2133

CL =

1866

CL = CL =

1866 1600

CL =

–

1600

CL =

1333

–

1333

–

RCD

CL = 9 (ns)

–

1333

–

1333

(ns)

46.16

45.32

46.16

46.5

14.16 14.16

13.32 13.32

14.16 14.16

13.5

PDF: 09005aef8519d7ca

asf9c512x72az.pdf – Rev. J 11/15 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4GB (x72, ECC, SR) 288-Pin DDR4 UDIMM

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4

modules. All pins listed may not be supported on this module. See Functional Block Di-

agram for pins specific to this module.

Table 5: Pin Descriptions

Symbol

Type

Input

Description

Address inputs:

Provide the row address for ACTIVATE commands and the column address for

READ/WRITE commands in order to select one location out of the memory array in the respec-

tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;

see individual entries in this table). The address inputs also provide the op-code during the

MODE REGISTER SET command. A17 is only defined for x4 SDRAM.

Auto precharge:

A10 is sampled during READ and WRITE commands to determine whether an

auto precharge should be performed on the accessed bank after a READ or WRITE operation

(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-

mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank

addresses.

Burst chop:

A12/BC_n is sampled during READ and WRITE commands to determine if burst

chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Com-

mand Truth Table in the DDR4 component data sheet.

Command input:

ACT_n defines the ACTIVATE command being entered along with CS_n. The

input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and

A14. See Command Truth Table.

Bank address inputs:

Define the bank (with a bank group) to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command.

Bank group address inputs:

Define the bank group to which a REFRESH, ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-

tions. x16-based SDRAM only has BG0.

Chip ID:

These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for

x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16

configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,

CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,

are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used

as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of

the command code.

Clock:

Differential clock inputs. All address, command, and control input signals are sampled

on the crossing of the positive edge of CK_t and the negative edge of CK_c.

Clock enable:

CKE HIGH activates and CKE LOW deactivates the internal clock signals, device

input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is

asynchronous for self refresh exit. After V

REFCA

has become stable during the power-on and ini-

tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE

must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,

CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE

and RESET#) are disabled during self refresh.

Chip select:

All commands are masked when CS_n is registered HIGH. CS_n provides external

rank selection on systems with multiple ranks. CS_n is considered part of the command code

(CS2_n and CS3_n are not used on UDIMMs).

A10/AP

Input

A12/BC_n

Input

ACT_n

Input

BAx

Input

BGx

Input

C0, C1, C2

(RDIMM/LRDIMM on-

ly)

Input

CKx_t

CKx_c

CKEx

Input

CSx_n

Input

PDF: 09005aef8519d7ca

asf9c512x72az.pdf – Rev. J 11/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MTA9ASF51272AZ-2G1B1 Related Products

	MTA9ASF51272AZ-2G1B1	MTA9ASF51272AZ-2G3B1	MTA9ASF51272AZ-2G6B1	MTA9ASF51272AZ-2G1A1
Description	IC SDRAM DDR4 4GB 512MX72 EUDIMM	MODULE DDR4 SDRAM 4GB 288UDIMM	MODULE DDR4 SDRAM 4GB 288UDIMM	IC SDRAM DDR4 512MX72 RDIMM
memory type	DDR4 SDRAM	DDR4 SDRAM	DDR4 SDRAM	DDR4 SDRAM
storage	4GB	4GB	4GB	4GB
speed	2133MT/s	2400MT/s	2666MT/s	2133MT/s
Package/casing	288-UDIMM	288-UDIMM	288-UDIMM	288-UDIMM

Recommended Resources

Transistor trigger circuit with sinusoidal synchronous reset control with RC positive feedback

Voltage controlled oscillator circuit composed of monostable circuit

Low voltage drop, high current voltage stabilizing circuit

Adjustable nonlinear ramp circuit diagram

555 high-precision linear voltage/frequency converter circuit

4 3/4-digit or 3-digit intelligent digital multimeter composed of MAxl33 and l 34

omapl138 shared memory, data transfer issues: [color=#000]我有关于omapl138共享内存，数据传输问题，请教。[/color] [color=#000]1. it can't write immediately to shared ram. code list delow: static bool server_upp_data_transfer(Server *server) {if(server->ad_started ==...; jackzhao DSP and ARM Processors

2014 Shenzhen Maker Fair concluded successfully: The two-day global Makers ' feast "2014 Shenzhen Maker Fair " came to a successful conclusion on April 7. Embest exhibited a series of new products at the exhibition, including BB-Black China Edition,...; oliverzhang DIY/Open Source Hardware

Principle and maintenance of electronic mosquito killer lamp: Principle and maintenance of electronic mosquito killer lamp　　Electronic mosquito killer lamps use low-power self-ballasted fluorescent tubes to induce mosquitoes according to the phototropism of mosq...; fighting Analog electronics

Great article! This explanation of ESD is so easy to understand!: [align=left][color=rgb(55, 74, 174)][size=13px]I have always wanted to tell you about the theory of ESD. It is very classic. However, since it is too theoretical, if you don’t understand the device th...; ohahaha PCB Design

Is there a problem with connecting an analog input terminal of the sampling chip AD7856 to the ground or power supply?: Has anyone encountered a situation where one of the analog inputs of the four-channel sampling chip AD7856 is grounded or connected to a 5V power supply? What is the purpose of this? Configuration or ...; zhangning029 ADI Reference Circuit

Should the board positioning holes be grounded?: In previous projects, the positioning holes were all grounded through a 1000pf/2kV capacitor. What was the purpose of doing this? A book I read recently said that using metal vias to reliably connect ...; xiaoxiao2211 Analog electronics

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components