4GB (x72, ECC, SR) 288-Pin DDR4 UDIMM
Features
DDR4 SDRAM UDIMM
MTA9ASF51272AZ – 4GB
Features
• DDR4 functionality and operations supported as de-
fined in the component data sheet
• 288-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC4-2600, PC4-2400, and
PC4-2133
• 4GB (512 Meg x 72)
• V
DD
= 1.20V (NOM)
• V
PP
= 2.5V (NOM)
• V
DDSPD
= 2.5V (NOM)
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die V
REFDQ
generation and calibration
• Single-rank
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Table 1: Key Timing Parameters
Data Rate (MT/s)
Industry
Speed Nomen-
Grade clature
-2G6
-2G4
-2G3
-2G1
PC4-2666
PC4-2400
PC4-2400
PC4-2133
CL =
20,
CL =
19
2666
–
–
–
Figure 1: 288-Pin UDIMM (MO-309, R/C D1)
Module height: 31.25mm (1.23in)
Options
• Operating temperature
– Commercial
(0°C
≤
T
OPER
≤
95°C)
• Package
– 288-pin DIMM (halogen-free)
• Frequency/CAS latency
– 0.75ns @ CL = 19 (DDR4-2666)
– 0.83ns @ CL = 17 (DDR4-2400)
– 0.93ns @ CL = 15 (DDR4-2133)
Marking
None
Z
-2G6
-2G3
-2G1
CL =
18
2666
2400
2400
–
CL =
17
2400
2400
2400
–
CL =
16
2133
2400
2133
2133
CL =
15
2133
2133
2133
2133
CL =
14
1866
1866
1866
1866
CL = CL =
13
12
1866 1600
1866 1600
1866 1600
1866 1600
CL =
11
–
1600
1600
1600
CL =
10
1333
–
1333
–
t
RCD
t
RP
t
RC
CL = 9 (ns)
–
1333
–
1333
(ns)
(ns)
46.16
45.32
46.16
46.5
14.16 14.16
13.32 13.32
14.16 14.16
13.5
13.5
PDF: 09005aef8519d7ca
asf9c512x72az.pdf – Rev. J 11/15 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 288-Pin DDR4 UDIMM
Features
Table 2: Addressing
Parameter
Row address
Column address
Device bank group address
Device bank address per group
Device configuration
Module rank address
4GB
32K A[14:0]
1K A[9:0]
4 BG[1:0]
4 BA[1:0]
4Gb (512 Meg x 8), 16 banks
CS0_n
Table 3: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT40A512M8,
1
4Gb DDR4 SDRAM
Module
2
Part Number
Density
MTA9ASF51272AZ-2G6__
MTA9ASF51272AZ-2G3__
MTA9ASF51272AZ-2G1__
Notes:
4GB
4GB
4GB
Module
Bandwidth
21.3 GB/s
19.2 GB/s
17.0 GB/s
Memory Clock/
Data Rate
0.75ns/2666 MT/s
0.83ns/2400 MT/s
0.93ns/2133 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
19-19-19
17-17-17
15-15-15
Configuration
512 Meg x 72
512 Meg x 72
512 Meg x 72
1. The data sheet for the base device can be found at
micron.com.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MTA9ASF51272AZ-2G6B1.
PDF: 09005aef8519d7ca
asf9c512x72az.pdf – Rev. J 11/15 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 288-Pin DDR4 UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Di-
agram for pins specific to this module.
Table 5: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respec-
tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
Auto precharge:
A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-
mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
Burst chop:
A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Com-
mand Truth Table in the DDR4 component data sheet.
Command input:
ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
Bank address inputs:
Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
Bank group address inputs:
Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-
tions. x16-based SDRAM only has BG0.
Chip ID:
These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
Clock:
Differential clock inputs. All address, command, and control input signals are sampled
on the crossing of the positive edge of CK_t and the negative edge of CK_c.
Clock enable:
CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After V
REFCA
has become stable during the power-on and ini-
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET#) are disabled during self refresh.
Chip select:
All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
A10/AP
Input
A12/BC_n
Input
ACT_n
Input
BAx
Input
BGx
Input
C0, C1, C2
(RDIMM/LRDIMM on-
ly)
Input
CKx_t
CKx_c
CKEx
Input
Input
CSx_n
Input
PDF: 09005aef8519d7ca
asf9c512x72az.pdf – Rev. J 11/15 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.
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