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MT48LC32M4A2P-7E:G

Description
IC DRAM 128M PARALLEL 54TSOP
Categorystorage    storage   
File Size995KB,86 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT48LC32M4A2P-7E:G Overview

IC DRAM 128M PARALLEL 54TSOP

MT48LC32M4A2P-7E:G Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee3
length22.22 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.33 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
128Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 Banks
MT48LC16M8A2 – 4 Meg x 8 x 4 Banks
MT48LC8M16A2 – 2 Meg x 16 x 4 Banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh modes: Standard and low power
(not available on AT devices)
• Auto Refresh
– 64ms, 4096-cycle refresh (commercial and
industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 60-ball TFBGA (8mm x 16mm)
– 60-ball TFBGA (8mm x 16mm) Pb-
free
– 54-ball VFBGA (x16 only) (8mm x
8mm)
– 54-ball VFBGA (x16 only) (8mm x
8mm) Pb-free
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
• Self refresh
– Standard
– Low power
• Revision
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
Notes:
1. Contact Micron for availability.
2. Off-center parting line.
3. Only available on Revision G.
Marking
TG
P
FB
1
BB
1
F4
B4
-75
3
-7E
-6A
None
L
3
:G/:L
None
IT
AT
1
Options
• Configurations
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
1
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
t
WR = 2 CLK
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-75
-7E
Clock
Frequency (MHz)
167
133
133
Marking
32M4
16M8
8M16
A2
Target
t
RCD-
t
RP-CL
3-3-3
3-3-3
2-2-2
t
RCD
(ns)
t
RP
(ns)
CL (ns)
18
20
15
18
20
15
18
20
15
PDF: 09005aef8091e66d
128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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