• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh modes: Standard and low power
(not available on AT devices)
• Auto Refresh
– 64ms, 4096-cycle refresh (commercial and
industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 60-ball TFBGA (8mm x 16mm)
– 60-ball TFBGA (8mm x 16mm) Pb-
free
– 54-ball VFBGA (x16 only) (8mm x
8mm)
– 54-ball VFBGA (x16 only) (8mm x
8mm) Pb-free
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
• Self refresh
– Standard
– Low power
• Revision
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
Notes:
1. Contact Micron for availability.
2. Off-center parting line.
3. Only available on Revision G.
Marking
TG
P
FB
1
BB
1
F4
B4
-75
3
-7E
-6A
None
L
3
:G/:L
None
IT
AT
1
Options
• Configurations
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
1
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
–
t
WR = 2 CLK
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-75
-7E
Clock
Frequency (MHz)
167
133
133
Marking
32M4
16M8
8M16
A2
Target
t
RCD-
t
RP-CL
3-3-3
3-3-3
2-2-2
t
RCD
(ns)
t
RP
(ns)
CL (ns)
18
20
15
18
20
15
18
20
15
PDF: 09005aef8091e66d
128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x4, x8, x16 SDRAM
Features
Table 2: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
2K A[9:0], A11
16 Meg x 8
4 Meg x 8 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
1K A[9:0]
8 Meg x 16
2 Meg x 16 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
512 A[8:0]
Table 3: 128Mb SDR Part Numbering
Part Numbers
MT48LC32M4A2TG
MT48LC32M4A2P
MT48LC16M8A2TG
MT48LC16M8A2P
MT48LC16M8A2FB
MT48LC16M8A2BB
MT48LC8M16A2TG
MT48LC8M16A2P
MT48LC8M16A2B4
MT48LC8M16A2F4
Note:
1. FBGA Device Decoder:
www.micron.com/decoder
Architecture
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
8 Meg x 16
16 Meg x 16
PDF: 09005aef8091e66d
128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 8
ACTIVE ...................................................................................................................................................... 32
Truth Tables ................................................................................................................................................... 37
Burst Type .................................................................................................................................................. 46
CAS Latency ............................................................................................................................................... 48
Auto Precharge ........................................................................................................................................... 67
AUTO REFRESH Operation ............................................................................................................................. 79
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