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SI5023

Description
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER
File Size734KB,28 Pages
ManufacturerSILABS
Websitehttp://www.silabs.com
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SI5023 Overview

MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
M
ULTI
-R
ATE
SONET/SDH CDR IC
WITH
L
IMITING
A
MPLIFIER
Features
H
igh-speed clock and data recovery device with integrated limiting amp:
Supports OC-48/12/3, STM-16/4/
Bit error rate alarm
1, Gigabit Ethernet, and 2.7 Gbps
Reference and referenceless
FEC
operation supported
Loss-of-signal level alarm
DSPLL
®
technology
Data slicing level control
Jitter generation 3.0 mUI
rms
10 mV
PP
differential sensitivity
(TYP)
Small footprint: 5 x 5 mm
3.3 V supply
Ordering Information:
See page 25.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Gigabit Ethernet interfaces
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Board level serial links
Pin Assignments
Si5023
BER_ALM
CLKOUT+
23
Description
RATESEL0
1
2
3
4
5
6
7
28
27
26
25
24
CLKOUT–
22
21
20
CLKDSBL
BERMON
BER_LVL
VDD
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
GND
The Si5023 is a fully-integrated, high-performance limiting amp and clock
and data recovery (CDR) IC for high-speed serial communication systems.
It derives timing information and data from a serial input at OC-48/12/3,
STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL
®
technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
The Si5023 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
GND
Pad
19
18
17
16
15
8
9
10
11
12
13
14
LOS
DIN+
DIN–
LTR
VDD
Top View
Functional Block Diagram
LOS_LVL
LOS
Signal
Detect
Retimer
DSQLCH
BUF
2
DOUT+
DOUT–
DIN+
DIN–
2
Limiting
Amp
DSPLL
BER
Monitor
BUF
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
2
Bias Gen.
Reset/
Calibration
BER_ALM
BERMON
SLICE_LVL
LTR
BER_LVL
LOL
RATESEL
REXT
RESET/CAL
Rev. 1.25 10/05
Copyright © 2005 by Silicon Laboratories
DSQLCH
VDD
Si5023

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Description MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER
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Index Files: 1656  1752  2353  2383  947  34  36  48  20  22 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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