IS61NLF25618EC-7.5TQLI-TR datasheet, PDF

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IS61NLF25618EC-7.5TQLI-TR: DescriptionIC SRAM 4.5M PARALLEL 100LQFP; Categorystorage; File Size2MB，40 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/; Environmental Compliance

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IS61NLF25618EC-7.5TQLI-TR Overview

IC SRAM 4.5M PARALLEL 100LQFP

IS61NLF25618EC-7.5TQLI-TR Parametric

Parameter Name	Attribute value
memory type	Volatile
memory format	SRAM
technology	SRAM - Synchronous
storage	4.5Mb （256K x 18）
Clock frequency	117MHz
Write cycle time - words, pages	-
interview time	7.5ns
memory interface	in parallel
Voltage - Power	3.135 V ~ 3.465 V
Operating temperature	-40°C ~ 85°C（TA）
Installation type	surface mount
Package/casing	100-LQFP
Supplier device packaging	100-LQFP（14x20）

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IS61(4)NLF12836EC/IS61(4)NVF12836EC/IS61(4)NLF12832EC

IS61(4)NVF12832EC/IS61(4)NLF25618EC/IS61(4)NVF25618EC

128K x36/32 and 256K x18 4Mb, ECC, FLOW THROUGH 'NO WAIT'

STATE BUS SYNCHRONOUS SRAM

APRIL 2017

FEATURES

•

100 percent bus utilization

•

No wait cycles between Read and Write

•

Internal self-timed write cycle

•

Individual Byte Write Control

•

Single R/W (Read/Write) control pin

•

Clock controlled, registered address, data and

control

•

Interleaved or linear burst sequence control

using MODE input

•

Three chip enables for simple depth

expansion and address pipelining

•

Power Down mode

•

Common data inputs and data outputs

•

/CKE pin to enable clock and suspend

operation

•

JEDEC 100-pin QFP, 165-ball BGA and 119-

ball BGA packages

•

Power supply:

NLF: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

NVF: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

•

JTAG Boundary Scan for BGA packages

•

Industrial and Automotive temperature support

•

Lead-free available

•

Error Detection and Error Correction

DESCRIPTION

The 4Mb product family features high-speed, low-

power synchronous static RAMs designed to

provide a burstable, high-performance, 'no wait'

state, device for networking and communications

applications. They are organized as 128K words

by 36 bits and 256K words by 18 bits, fabricated

with

ISSI's

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles

are eliminated when the bus switches from read

to write, or write to read. This device integrates a

2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single

monolithic circuit.

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single

clock input. Operations may be suspended and all

synchronous inputs ignored when Clock Enable,

/CKE is HIGH. In this state the internal device will

hold their previous values.

All Read, Write and Deselect cycles are initiated

by the ADV input. When the ADV is HIGH the

internal burst counter is incremented. New

external addresses can be loaded when ADV is

LOW.

Write cycles are internally self-timed and are

initiated by the rising edge of the clock inputs and

when /WE is LOW. Separate byte enables allow

individual bytes to be written.

A burst mode pin (MODE) defines the order of the

burst sequence. When tied HIGH, the interleaved

burst sequence is selected. When tied LOW, the

linear burst sequence is selected.

-6.5

6.5

7.5

133

FAST ACCESS TIME

Symbol

tKQ

tKC

Parameter

Clock Access Time

Cycle time

Frequency

-7.5

7.5

8.5

117

Units

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. C2

04/21/2017

IS61NLF25618EC-7.5TQLI-TR Related Products

	IS61NLF25618EC-7.5TQLI-TR	IS61NLF12836EC-7.5TQLI	IS61NLF25618EC-7.5TQLI	IS61NLF12836EC-7.5TQLI-TR
Description	IC SRAM 4.5M PARALLEL 100LQFP	IC SRAM 4.5M PARALLEL 100LQFP	ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100	IC SRAM 4.5M PARALLEL 100LQFP
technology	SRAM - Synchronous	SRAM - Synchronous	CMOS	SRAM - Synchronous
memory type	Volatile	Volatile	-	Volatile
memory format	SRAM	SRAM	-	SRAM
storage	4.5Mb （256K x 18）	4.5Mb （128K x 36）	-	4.5Mb （128K x 36）
Clock frequency	117MHz	117MHz	-	117MHz
interview time	7.5ns	7.5ns	-	7.5ns
memory interface	in parallel	in parallel	-	in parallel
Voltage - Power	3.135 V ~ 3.465 V	3.135 V ~ 3.465 V	-	3.135 V ~ 3.465 V
Operating temperature	-40°C ~ 85°C（TA）	-40°C ~ 85°C（TA）	-	-40°C ~ 85°C（TA）
Installation type	surface mount	surface mount	-	surface mount
Package/casing	100-LQFP	100-LQFP	-	100-LQFP
Supplier device packaging	100-LQFP（14x20）	100-LQFP（14x20）	-	100-LQFP（14x20）

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