Si3233
P
R O
SLIC
®
P
R O G R A M M A B L E
CMOS SLIC
W I T H
R
I N G I N G
/ B
A T T E R Y
V
O L TA G E
G
E N E R A T I O N
Features
Software Programmable SLIC with
codec interface
Software programmable internal
balanced ringing up to 90 V
PK
(5 REN up to 4 kft, 3 REN up to 8 kft)
Integrated battery supply with dynamic
voltage output
On-chip dc-dc converter continuously
minimizes power in all operating modes
Entire solution can be powered from a
single 3.3 V or 5 V supply
3.3 V to 35 V dc input range
Dynamic 0 V to –94.5 V output
Software programmable signal
generation and audio processing:
Phase-continuous FSK (caller ID)
generation
Dual audio tone generators
Smooth and abrupt polarity reversal
Extensive test and diagnostic
features
Realtime dc linefeed measurement
GR-909 line test capabilities
Ordering Information
See page 95.
Software programmable linefeed
parameters:
Ringing frequency, amplitude, cadence,
and waveshape
2-wire ac impedance
constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds and
filtering
SPI control interface
Extensive programmable interrupts
100% software configurable global
solution
Lead-Free and RoHS-compliant
Pin Assignments
QFN Package
TEST2
PCLK
INT
CS
SCLK
SDI
SDO
Applications
Interface to Broadcom devices
BCM11xx residential gateway
BCM3341 VOIP processor
BCM33xx cable modem
Voice over IP
Terminal adapters
Fixed cellular terminal
Description
The Si3233 ProSLIC
®
is a low-voltage CMOS device that provides a multi-functional
subscriber line interface ideal for customer premise equipment (CPE) applications.
The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation
functionality into a single CMOS integrated circuit. The integrated battery supply
continuously adapts its output voltage to minimize power and enables the entire
solution to be powered from a single 3.3 V (Si3233M only) or 5 V supply. The ProSLIC
controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry.
Si3233 features include software-configurable 5 REN internal ringing up to 90 V
PK
,
DTMF generation, and a comprehensive set of telephony signaling capabilities for
operation with only one hardware solution. The ProSLIC is packaged in a 38-pin QFN
and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC.
NC
FSYNC
RESET
SDCH
SDCL
V
DDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
1 38 37 36 35 34 33 32 31
30
2
3
4
5
6
7
8
9
10
11
29
28
27
26
25
24
23
22
21
12 13 14 15 16 17 18 19 20
SDITHRU
DCDRV
DCFF
TEST1
GNDD
VDDD
ITIPN
ITIPP
V
DDA2
IRINGP
IRINGN
IGMP
Patents pending
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
Functional Block Diagram
INT RESET
SPI Control Interface
CS
SCLK
SDO
SDI
Si3233
Ringing Generator
Loop Closure Detect
Ring Trip Detect Line
Diagnostics
SLIC
Linefeed Control
Linefeed Monitor
Linefeed
Interface
Tip
Ring
Tone Generators
FSK Caller ID
Impedance Synth
PCLK
PLL
FSYNC
DC–DC Converter Controller
Battery
Preliminary Rev. 0.5 4/06
Copyright © 2006 by Silicon Laboratories
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
Si3233
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3233
2
Preliminary Rev. 0.5
Si3233
T
A B L E O F
C
O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1. Si3230 to Si3233 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.8. PLL Free-run Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5. Pin Descriptions: Si3233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Preliminary Rev. 0.5
3
Si3233
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
DC Supply Voltage
Input Current, Digital Input Pins
Digital Input Voltage
Operating Temperature Range
2
Storage Temperature Range
TSSOP-38 Thermal Resistance, Typical
QFN-38 Thermal Resistance, Typical
Continuous Power Dissipation
2
Si3201
DC Supply Voltage
Battery Supply Voltage
Input Voltage: TIP, RING, SRINGE, STIPE pins
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins
Operating Temperature Range
2
Storage Temperature Range
SOIC-16 Thermal Resistance, Typical
3
Continuous Power Dissipation
2
V
DD
V
BAT
V
INHV
V
IN
T
A
T
STG
θ
JA
P
D
–0.5 to 6.0
–104
(V
BAT
– 0.3) to (V
DD
+ 0.3)
–0.3 to (V
DD
+ 0.3)
–40 to 100
–40 to 150
55
1.0
V
V
V
V
ºC
ºC
ºC/W
W
Symbol
Si3233
V
DDD
, V
DDA1
, V
DDA2
I
IN
V
IND
T
A
T
STG
θ
JA
θ
JA
P
D
–0.5 to 6.0
±10
–0.3 to (V
DDD
+ 0.3)
–40 to 100
–40 to 150
70
35
0.7
V
mA
V
ºC
ºC
ºC/W
ºC/W
W
Value
Unit
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2.
Operation above 125
o
C junction temperature may degrade device reliability.
3.
Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
4
Preliminary Rev. 0.5
Si3233
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Ambient Temperature
Si3233 Supply Voltage
Si3201 Supply Voltage
Si3201 Battery Voltage
Symbol
T
A
T
A
V
DDD
,V
DDA1
,V
DDA2
V
DD
V
BAT
V
BATH
= V
BAT
Test Condition
F-grade
G-grade
Min*
0
–40
3.13
3.13
–96
Typ
25
25
3.3/5.0
3.3/5.0
—
Max*
70
85
5.25
5.25
–10
Unit
o
C
o
C
V
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25
o
C unless otherwise stated.
Product specifications are only guaranteed when the typical application circuit (including component tolerances) is
used.
Table 3. AC Characteristics
(V
DDA
, V
DDD
= 3.13 to 5.25 V, T
A
= 0 to 70°C for F-Grade, –40 to 85°C for G-Grade)
Parameter
Overload Level
Audio Tone Generator
Signal-to-Distortion Ratio
1
Intermodulation Distortion
2-Wire Return Loss
Idle Channel Noise
2
Test Condition
TX/RX Performance
THD = 1.5%
0 dBm0, Active off-hook,
and OHT, any Zac
200 Hz to 3.4 kHz
Noise Performance
C-Message Weighted
Psophometric Weighted
3 kHz flat
Min
2.5
45
—
30
—
—
—
40
40
40
56
43
53
53
40
Typ
—
—
—
35
—
—
—
—
—
—
60
60
60
60
—
Max
—
—
–45
—
15
–75
18
—
—
—
—
—
—
—
—
Unit
V
PK
dB
dB
dB
dBrnC
dBmP
dBrn
dB
dB
dB
dB
dB
dB
dB
dB
PSRR from VDDA
PSRR from VDDD
PSRR from VBAT
Longitudinal to Metallic Balance
RX and TX, DC to 3.4 kHz
RX and TX, DC to 3.4 kHz
RX and TX, DC to 3.4 kHz
Longitudinal Performance
200 Hz to 3.4 kHz,
β
Q1,Q2
≥
150, 1% mismatch
β
Q1,Q2
=
60 to 240
3
β
Q1,Q2
=
300 to 800
3
Using Si3201
Metallic to Longitudinal Balance
200 Hz to 3.4 kHz
Notes:
1.
Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2.
The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
3.
Assumes normal distribution of betas.
Preliminary Rev. 0.5
5
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