XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
JULY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR19L200 (L200) is a highly integrated device that
combines a single channel Universal Asynchronous
Receiver and Transmitter (UART) and an RS-232
transceiver. The L200 is designed to operate with a single
3.3V or 5V power supply. The L200 is fully compliant with
EIA/TIA-232-F Standards from a +3.0V to +5.5V power
supply. The device operates at 250 Kbps data rate with
worst case 3K ohms load. Both RS-232 driver outputs and
receiver inputs can operate in harsh electrical environments
of +/-15V without damage and can survive multiple +/-15kV
ESD on the RS-232 lines, while maintaining RS-232 output
levels.
The L200 operates in three different modes: Awake, Partial
Sleep, and Full Sleep. Each mode can be invoked via
hardware or software. In the Awake mode, all functions are
active. In the Partial Sleep mode, the internal crystal
oscillator or charge pump is turned off. In Full Sleep mode,
the internal crystal oscillator and the charge pump is shut
down. All the RS-232 receivers remain active in any of
these four modes.
APPLICATIONS
•
Battery-Powered Equipment
•
Handheld and Mobile Devices
•
Handheld Terminals
•
Industrial Peripheral Interfaces
•
Point-of-Sale (POS) Systems
FEATURES
•
Meets true EIA/TIA-232-F Standards from a 3.0 V to 5.5V
operation
•
Up to 250 Kbps data transmission rate
•
45us sleep mode exit (charge pump to full power)
•
ESD protection for RS-232 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/-15kV - IEC 61000-4-2, Air-Gap Discharge
+/- 8kV - IEC 61000-4-2, Contact Discharge
•
Software compatible with industry standard 16550 UART
•
Intel/Motorola bus select
•
Quarter-modem interface (TXD, RXD)
•
Sleep modes to conserve battery power
•
Wake-up interrupt upon exiting low power modes
F
IGURE
1. B
LOCK
D
IAGRAM
VCC
(3.0 to 5.5V)
XTAL1
XTAL2
GND
ACP
C2+
C1+
C2-
C1-
VREF+
Crystal
Osc/Buffer
BRG
Charge Pump
VREF-
TX
RX
5K
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS#
INT (IRQ#)
RESET (RESET#)
I/M#
*5 V
Tolerant
Inputs
Intel or Motorola Bus Interface
UART Registers
16 Byte
TX FIFO
16 Byte
RX FIFO
TXD
RXD
Modem
I/Os
UART
XR19L200
RS-232 Transceiver
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
VCC
VREF+
VCC
VREF+
C1 -
C 1+
RESET#
GND
IRQ#
A0
A1
A2
VREF -
REV. 1.0.2
C1 -
D4
D3
D2
D1
D0
D4
C1+
RESET
GND
INT
A0
A1
A2
VREF-
GND
RXD
I/M#
D5
GND
D6
D7
CS#
TXD
1
2
3
4
5
6
7
8
D3
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
24
23
22
Motorola Bus Mode
21
20
32-pin QFN
19
18
17
VCC
RXD
I/M#
D5
GND
D6
D7
CS#
TXD
1
2
3
4
5
6
7
8
XR19L200
Intel Bus Mode
32-pin QFN
24
23
22
21
20
19
18
17
XR19L200
9 10 11 12 13 14 15 16
9 10 11 12 13 14 15 16
XTAL1
XTAL2
IOW#
ACP
GND
IOR#
C2+
C2-
XTAL1
XTAL2
R/W#
ACP
GND
NC
C2+
D2
D1
D0
ORDERING INFORMATION
P
ART
N
UMBER
XR19L200IL32
P
ACKAGE
32-QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
C2-
XR19L200
REV. 1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
N
AME
32-QFN
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(NC)
18
19
20
6
5
3
32
31
30
29
28
14
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
This input is chip select (active LOW) to enable the device.
IOW#
(R/W#)
11
I
CS#
INT
(IRQ#)
7
21
I
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH device interrupt output. This output is enabled through the software setting of MCR[3]:
set to the active mode when MCR[3] is set to a logic 1, and set to the three state mode when
MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output. An external pull-up resistor is required for proper opera-
tion. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
TXD
RXD
8
1
O
I
UART Transmit Data. The TX signal will be LOW (< -5V) during reset or idle (no data).
UART Receive Data. The RX data input must idle LOW (< -3V).
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
XTAL2
ACP
9
10
12
I
O
I
Crystal or external clock input. This input is not 5V tolerant.
Crystal or buffered clock output. This output may be use to drive a clock buffer which can
drive other device(s).
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the L200 is already in partial sleep mode, i.e. the crystal oscillator is stopped.
3
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
Pin Descriptions
N
AME
I/M#
32-QFN
PIN#
2
T
YPE
I
D
ESCRIPTION
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see
Table 11
).
Charge pump capacitors. As shown in
Figure 1
, a 0.1 uF capacitor should be placed
between these 2 pins.
Charge pump capacitors. As shown in
Figure 1
, a 0.1 uF capacitor should be placed
between these 2 pins.
REV. 1.0.2
RESET
(RESET#)
23
I
C2+
C2-
C1+
C1-
VREF+
VREF-
VCC
GND
GND
15
16
24
25
26
17
27
13
-
-
-
Pwr +5.0V generated by the charge pump.
Pwr -5.0V generated by the charge pump.
Pwr 3.0V to 5.5V power supply. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the 32-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
NC
-
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
input voltage levels, ’LOW’ is any voltage < -3V and ’HIGH’ is any voltage > 3V. For RS-232 output voltage levels,
’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V.
4
XR19L200
REV. 1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
1.0 PRODUCT DESCRIPTION
The XR19L200 interface converter consists of a full-functional UART with 16 bytes of transmit and receive
FIFO, a charge pump, two RS-232 drivers, two RS-232 receivers, and a sleep mode circuitry. It operates from
a single +3V to 5.5V supply at 250Kbps data rate, while meeting all EIA RS-232F specifications. Its feature set
is fully compatible to the XR16L580 device. Unlike the XR16L580, the modem signals are not CMOS/TTL
level, but conform to EIA/TIA 232 or RS-232 voltage levels. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Also, the L200 has 16-bytes of transmit and receive FIFOs,
automatic Xon/Xoff and special character software flow control, transmit and receive FIFO trigger levels, and a
programmable baud rate generator with a prescaler of divide by 1 or 4. Additionally, the L200 includes the ACP
pin which the user can shut down the charge pump for the RS-232 drivers when the L200 is already in sleep
mode. The L200 is fabricated using an advanced CMOS process.
Enhanced Features
The L200 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L200 is
designed to work with low supply voltage and high performance data communication systems that require fast
data processing time. Increased performance is realized in the L200 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time.
Intel or Motorola Data Bus Interface
The L200 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, I/M#.
Data Rate
The L200 is capable of operation up to 250Kbps data rate using the 16X internal sampling clock rate. The
UART section can operate at much higher speeds, but the speed of the RS-232 transceiver is limited to
250Kbps beyond which the L200 cannot comply with the EIA/TIA-232 electrical characteristics. The device can
operate either with a crystal on pins XTAL1 and XTAL2, or external clock source on XTAL1 pin.
Internal Enhanced Register Sets
The L200 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, modem interface controls and status, and
sleep mode are all standard features. Following a power on reset or an external reset (and operating in 16 or
Intel Mode), the registers defaults to the reset condition and is compatible with the XR16L580.
RS-232 Interface
The L200 includes RS-232 drivers/receivers for the TXD and RXD signals (If more modem input and output
signals are needed, see the XR19L220 and XR19L210). This feature eliminates the need for an external RS-
232 transceiver. The charge pump provides output voltages of +5V and -5V for its drivers over the 3.0V to 5.5V
VCC supply voltage. The serial output TX swings between -5V (inactive) and 5V (active) RS-232 voltage
levels. The serial input RX is an RS-232 receiver and can take any voltage swing from -15V to +15V. The
receiver is always active, even in Partial or Full Sleep modes. The RS-232 drivers guarantee a data rate of
250Kbps even when fully loaded with 3Kohm in parallel with 1000pF load. Also, the slew rate of the driver
output is internally limited to a maximum of 30V/us in order to meet the EIA-232F standard.
5
京公网安备 11010802033920号
EEWORLD
