Freescale Semiconductor
Data Sheet
Document Number: SCF5249EC
Rev.
0,
04/2005
SCF5249 Integrated ColdFire®
Microprocessor Data Sheet
1
Introduction
Table of Contents
1
2
3
4
5
6
7
8
9
10
Introduction..........................................................1
SCF5249 Block Diagram .....................................3
SCF5249 Feature Details ....................................3
160 MAPBGA Ball Assignments .........................6
SCF5249 Functional Overview............................7
General Device Information...............................12
Documentation ..................................................12
Signal Descriptions............................................13
Electrical Characteristics ...................................28
Pin-Out and Package Information .....................46
This document provides an overview of the SCF5249
ColdFire
®
processor and general descriptions of
SCF5249 features and its various modules.
The SCF5249 was designed as a system
controller/decoder for MP3 music players, especially
portable MP3 CD players. The 32-bit ColdFire core with
Enhanced Multiply Accumulate (EMAC) unit provides
optimum performance and code density for the
combination of control code and signal processing
required for MP3 decode, file management, and system
control.
Low power features include a hardwired CD ROM
decoder, advanced 0.18um CMOS process technology,
1.8V core power supply, and on-chip 96KByte SRAM.
MP3 decode requires less than 20MHz CPU bandwidth
and runs in on-chip SRAM with external access only for
data input and output.
The SCF5249 is also an excellent general purpose
system controller with over 125 Dhrystone 2.1 MIPS @
140MHz performance at a very competitive price. The
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Introduction
integrated peripherals and EMAC allow the SCF5249 to replace both the microcontroller and the DSP in
certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins.
1.1
1.1.1
Orderable Parts Numbers
Orderable Part Table
Table 1. Orderable Part Numbers
Orderable Part
Number
Maximum Clock
Frequency
120 MHz
120 MHz
140 MHz
140 MHz
Package Type
144 pin QFP
144 pin QFP
160 ball MAPBGA
160 ball MAPBGA
Operating
Temperature Range
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
Part Status
Leaded
Lead Free
Leaded
Lead Free
SCF5249LPV120
SCF5249LAG120
SCF5249VF140
SCF5249VM140
1.2
SCF5249 Features
The SCF5249 integrated microprocessor combines a Version 2 ColdFire
®
processor core operating at
140MHz with the following modules.
• DMA controller with 4 DMA channels
• Integrated Enhanced Multiply-accumulate Unit (EMAC)
• 8-KByte Direct Mapped Instruction Cache
• 96-KByte SRAM (A 64K and a 32K bank)
• Operates from external crystal oscillator
• Supports 16-bit wide SDRAM memories
• Serial Audio Interface which supports IIS and EIAJ audio protocols
• Digital audio transmitter and two receivers compliant with IEC958 audio protocol
• CD-ROM and CD-ROM XA block decoding and encoding function
• Two UARTS
• Queued Serial Peripheral Interface (QSPI) (Master Only)
• Two timers
• IDE and SmartMedia interfaces
• Analog/Digital Converter
• Flash Memory Card Interface
• Two I
2
C modules
•
•
System debug support
General Purpose I/O pins shared with other functions
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
2
Freescale Semiconductor
SCF5249 Block Diagram
•
•
•
1.8V core, 3.3V I/O
160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at 120
MHz)
-20
0
C to 70
0
C ambient operating temperature range
2
SCF5249 Block Diagram
CD ROM
Block
Decoder
Encoder
CD Text
Interface
QSPI
12-bit ADC
DUART
8K
byte
I-Cache
ColdFire V2
I Addr Gen
I Fetch
B
u
s
C
o
n
t
r
o
l
Serial Audio
Interface
3 x I
2
S Rx
2 x I
2
S Tx
96K
Byte
SRAM
Instr Buf
Dec&Sel Op
A Gen & Ex
SPDIF/EBU
Transmitter
IDE
Interface
Flash
Media
Interface
EMAC
Debug
Module
M-bus
(I
2
C)
Timers
SDRAM
Cntr
& Chip
Selects
General
Purpose
I/O
SPDIF/EBU
Receiver
DMA
PLL
Frequency
Synthesizer
Figure 1. SCF5249 Block Diagram
3
SCF5249 Feature Details
The primary features of the SCF5249 integrated processor include the following:
• ColdFire V2 Processor Core operating at 140MHz
— Clock-doubled Version 2 microprocessor core
— 32-bit internal data bus, 16 bit external data bus
— 16 user-visible, 32-bit general-purpose registers
— Supervisor/user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high-level language constructs
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
3
SCF5249 Feature Details
•
DMA controller
— Four fully programmable channels: Two dedicated to the audio interface module and two
dedicated to the UART module (External requests are not supported.)
— Supports dual- and single-address transfers with 32-bit data capability
— Two address pointers that can increment or remain constant
—
—
—
—
—
—
—
16-/24-bit transfer counter
Operand packing and unpacking support
Auto-alignment transfers supported for efficient block movement
Supports bursting and cycle stealing
All channels support memory to memory transfers
Interrupt capability
Provides two clock cycle internal access
•
•
•
•
•
Enhanced Multiply-accumulator Unit
— Single-cycle multiply-accumulate operations for 32 x 32 bit and 16 x 16 bit operands
— Support for signed, unsigned, integer, and fixed-point fractional input operands
— Four 48-bit accumulators to allow the use of a 40-bit product
— The addition of 8 extension bits to increase the dynamic number range
— Fast signed and unsigned integer multiplies
8-KByte Direct Mapped instruction cache
— Clock-doubled to match microprocessor core speed
— Flush capability
— Non-blocking cache provides fast access to critical code and data
96-KByte SRAM
— Provides one-cycle access to critical code and data
— Split into two banks, SRAM0 (32K), and SRAM1 (64K)
— DMA requests to/from internal SRAM1 supported
Crystal Trim
— The XTRIM output can be used to trim an external crystal oscillator circuit which would
allow lock with an incoming IEC958 or serial audio signal
Audio Interfaces
— IEC958 input and output
— Four serial Philips IIS/Sony EIAJ interfaces
– One with input and output, one with output only, two with input only (Three inputs, two
outputs)
– Master and Slave operation
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
4
Freescale Semiconductor
SCF5249 Feature Details
•
•
•
•
•
•
•
•
CD Text Interface
— Allows the interface of CD subcode (transmitter only)
Dual Universal Synchronous/asynchronous Receiver/Transmitter (Dual UART)
— Full duplex operation
— Baud-rate generator
— Modem control signals: clear-to-send (CTS) and request-to-send (RTS)
— DMA interrupt capability
— Processor-interrupt capability
Queued Serial Peripheral Interface (QSPI)
— Programmable queue to support up to 16 transfers without user intervention
— Supports transfer sizes of 8 to 16 bits in 1-bit increments
— Four peripheral chip-select lines for control of up to 15 devices
— Baud rates from 273 Kbps to 17.5 Mbps at 140MHz
— Programmable delays before and after transfers
— Programmable clock phase and polarity
— Supports wraparound mode for continuous transfers
— Master mode only
Dual 16-bit General-purpose Multimode Timers
— Clock source selectable from external, CPU clock/2 and CPU clock/32.
— 8-bit programmable prescaler
— 2 timer inputs and 2 outputs
— Processor-interrupt capability
— 14.3 nS resolution with CPU clock at 140MHz
IDE/ SmartMedia Interface
— Allows direct connection to an IDE hard drive or other IDE peripheral
Analog/Digital Converter
— 12-Bit Resolution
— 4 Muxed inputs
Flash Memory Card Interface
— Allows connection to Sony MemoryStick compatible devices
— Support SD cards and other types of flash media
Dual I
2
C Interfaces
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads
— Master and slave modes, support for multiple masters
— Automatic interrupt generation with programmable level
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
5
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