DISCRETE SEMICONDUCTORS
DATA SHEET
BF1100WR
Dual-gate MOS-FET
Product specification
1995 Apr 25
NXP Semiconductors
Product specification
Dual-gate MOS-FET
FEATURES
Specially designed for use at 9 to 12 V supply voltage
Short channel transistor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz
Superior cross-modulation performance during AGC.
APPLICATIONS
VHF and UHF applications such as television tuners and
professional communications equipment.
DESCRIPTION
Enhancement type field-effect transistor in a plastic
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Marking code:
MF.
handbook, halfpage
BF1100WR
PINNING
PIN
1
2
3
4
SYMBOL
s, b
d
g
2
g
1
source
drain
gate 2
gate 1
DESCRIPTION
d
4
3
g2
g1
2
1
Top view
MAM192
s,b
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
y
fs
C
ig1-s
C
rs
F
drain current
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
f = 1 MHz
f = 800 MHz
PARAMETER
drain-source voltage
CONDITIONS
24
MIN.
28
2.2
25
2
TYP.
MAX.
14
30
280
150
33
2.6
35
UNIT
V
mA
mW
C
mS
pF
fF
dB
1995 Apr 25
2
NXP Semiconductors
Product specification
Dual-gate MOS-FET
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
see Fig.2; up to T
amb
= 50
C;
note 1
CONDITIONS
65
MIN.
BF1100WR
MAX.
14
30
10
10
280
+150
+150
V
UNIT
mA
mA
mA
mW
C
C
MLD180
MLD156
handbook, halfpage
300
40
Y fs
(mS)
30
Ptot
(mW)
200
20
100
10
0
0
50
100
150
200
o
Tamb ( C)
0
50
0
50
100
150
T j ( C)
o
Fig.3
Fig.2 Power derating curve.
Forward transfer admittance as a function
of junction temperature; typical values.
1995 Apr 25
3
NXP Semiconductors
Product specification
Dual-gate MOS-FET
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
R
th j-s
Notes
1. Device mounted on a printed-circuit board.
2. T
s
is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
C;
unless otherwise specified.
SYMBOL
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-S
= 1 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 1 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
G2-S
= 4 V; V
DS
= 9 V;
I
D
= 20
A
V
G2-S
= 4 V; V
DS
= 12 V;
I
D
= 20
A
V
G2-S(th)
gate 2-source threshold voltage
V
G1-S
= 4 V; V
DS
= 9 V;
I
D
= 20
A
V
G1-S
= 4 V; V
DS
= 12 V;
I
D
= 20
A
I
DSX
drain-source current
V
G2-S
= 4 V; V
DS
= 9 V;
R
G1
= 180 k; note 1
V
G2-S
= 4 V; V
DS
= 12 V;
R
G1
= 250 k; note 2
I
G1-SS
I
G2-SS
Notes
1. R
G1
connects gate 1 to V
GG
= 9 V; see Fig.26.
2. R
G1
connects gate 1 to V
GG
= 12 V; see Fig.26.
gate 1 cut-off current
gate 2 cut-off current
V
G2-S
= V
DS
= 0; V
G1-S
= 12 V
V
G1-S
= V
DS
= 0; V
G2-S
= 12 V
MIN.
13.2
13.2
0.5
0.5
0.3
0.3
0.3
0.3
8
8
PARAMETER
thermal resistance from junction to ambient
thermal resistance from junction to soldering point
CONDITIONS
note 1
T
s
= 91
C;
note 2
BF1100WR
VALUE
350
210
UNIT
K/W
K/W
MAX.
20
20
1.5
1.5
1
1
1.2
1.2
13
13
50
50
V
V
V
V
V
V
V
V
UNIT
mA
mA
nA
nA
1995 Apr 25
4
NXP Semiconductors
Product specification
Dual-gate MOS-FET
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C;
V
G2-S
= 4 V; I
D
= 10 mA; unless otherwise specified.
SYMBOL
y
fs
PARAMETER
forward transfer admittance
CONDITIONS
pulsed; T
j
= 25
C
V
DS
= 9 V
V
DS
= 12 V
C
ig1-s
input capacitance at gate 1
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
ig2-s
input capacitance at gate 2
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
os
drain-source capacitance
f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
C
rs
reverse transfer capacitance f = 1 MHz
V
DS
= 9 V
V
DS
= 12 V
F
noise figure
f = 800 MHz; G
S
= G
Sopt
; B
S
= B
Sopt
V
DS
= 9 V
V
DS
= 12 V
2
2
25
25
1.4
1.1
1.6
1.4
2.2
2.2
24
24
28
28
MIN.
TYP.
BF1100WR
MAX.
33
33
2.6
2.6
1.8
1.5
35
35
2.8
2.8
UNIT
mS
mS
pF
pF
pF
pF
pF
pF
fF
fF
dB
dB
MLD157
0
handbook, halfpage
gain
reduction
(dB)
10
handbook, halfpage
120
MLD158
Vunw
(dBμV)
110
(1)
(2)
20
100
30
90
40
50
0
1
2
3
VAGC (V)
4
80
0
10
20
30
40
50
gain reduction (dB)
f = 50 MHz.
T
j
= 25
C.
(1) R
G
= 250 k to V
GG
= 12 V.
(2) R
G
= 180 k to V
GG
= 9 V.
f
w
= 50 MHz; f
unw
= 60 MHz; T
amb
= 25
C.
Fig.5
Fig.4
Gain reduction as a function of the AGC
voltage; typical values.
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.26.
1995 Apr 25
5
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