GS8342D38BD-500 datasheet, PDF

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GS8342D38BD-500: DescriptionStatic random access memory 1.8 or 1.5V 1M x 36 36M; Categorystorage storage; File Size325KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8342D38BD-500 Overview

Static random access memory 1.8 or 1.5V 1M x 36 36M

GS8342D38BD-500 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	10 weeks
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	500 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.25 A
Minimum standby current	1.7 V
Maximum slew rate	1.115 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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GS8342D06/11/20/38BD-550/500/450/400/350

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) intputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

36Mb SigmaQuad-II+

Burst of 4 SRAM

550 MHz–350 MHz

1.8 V V

1.8 V or 1.5 V I/O

SRAMs. The GS8342D06/11/20/38BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342D06/11/20/38BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 4M x 8 has a 1M

addressable index).

SigmaQuad-II™ Family Overview

The GS8342D06/11/20/38BD are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

Parameter Synopsis

-550

tKHKH

tKHQV

1.81 ns

0.45 ns

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

Rev: 1.02c 8/2017

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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