Lead-
Free
Package
Options
Available!
ispLSI 2064/A
In-System Programmable High Density PLD
Functional Block Diagram
Input Bus
®
Features
• ENHANCEMENTS
— ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
— ispLSI 2064A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
Output Routing Pool (ORP)
S
B1
B7
B6
B5
B4
Select devices have been discontinued.
See Ordering Information section for product status.
Output Routing Pool (ORP)
D
A4
A5
A6
A7
Output Routing Pool (ORP)
Input Bus
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
Input Bus
A2
GLB
Logic
Array
D Q
D Q
D Q
A3
B0
Fu
N
EW
0139Bisp/2064
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
U
SE
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
LS
I2
06
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
4E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
is
p
FO
The ispLSI 2064 and 2064A are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…B7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
R
Description
August 2006
2064_10
1
Input Bus
A1
D Q
B2
Output Routing Pool (ORP)
• HIGH DENSITY PROGRAMMABLE LOGIC
A0
ES
IG
Global Routing Pool
(GRP)
N
B3
Specifications
ispLSI 2064/A
Functional Block Diagram
Figure 1. ispLSI 2064/A Functional Block Diagram
GOE 0
GOE 1
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
Input Bus
Generic Logic
Blocks (GLBs)
Megablock
B7
Output Routing Pool (ORP)
B6
B5
B4
S
Output Routing Pool (ORP)
Input Bus
Y0
Y1
Y2
Select devices have been discontinued.
See Ordering Information section for product status.
A1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
Input Bus
Global Routing Pool
(GRP)
EW
A7
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
A0
A2
N
FO
A3
R
A4
A5
A6
64
ispEN
Input Bus
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
20
I/O 28
I/O 29
I/O 30
I/O 31
pL
SI
U
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064 and 2064A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each ispLSI
2064 and 2064A device contains two Megablocks.
SE
is
2
CLK 0
CLK 1
CLK 2
RESET
Output Routing Pool (ORP)
E
D
ES
IG
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
SCLK/IN 3
SDO/IN 2
B3
B2
B1
B0
0139B(1)isp/2064
N
Specifications
ispLSI 2064/A
Absolute Maximum Ratings
1
Supply Voltage V
cc ...................................................
-0.5 to +7.0V
Input Voltage Applied .............................. -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ........... -2.5 to V
CC
+1.0V
Storage Temperature ..................................... -65 to 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
D
ES
IG
MIN.
4.75
4.5
0
2.0
UNITS
pf
pf
pf
Max. Junction Temp. (T
J
) with Power Applied ............ 150°C
N
MAX.
5.25
5.5
0.8
V
cc
+1
UNITS
V
V
V
V
Table 2 - 0005/2064
Case Temp. with Power Applied .................... -55 to 125°C
S
T
A
= -40°C to + 85°C
Select devices have been discontinued.
See Ordering Information section for product status.
64
E
TYPICAL
8
9
15
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
FO
V
IL
V
IH
R
N
V
CC
T
A
= 0°C to + 70°C
PARAMETER
TEST CONDITIONS
V
CC
= 5.0V, V
IN
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2-0006/2064
Data Retention Specifications
is
pL
PARAMETER
SI
C
1
C
2
C
3
I/O Capacitance
Clock Capacitance
20
Dedicated Input Capacitance
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008/2064
Erase/Reprogram Cycles
U
SE
Data Retention
3
Specifications
ispLSI 2064/A
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-125
Others
1.5V
1.5V
See Figure 2
Table 2-0003/2064
Figure 2. Test Load
+ 5V
R1
≤
2 ns
≤
3 ns
S
R2
CL
*
Device
Output
Test
Point
Select devices have been discontinued.
See Ordering Information section for product status.
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
C
Table 2-0004/2064
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
E
Over Recommended Operating Conditions
FO
R
N
EW
CONDITION
MIN.
–
2.4
–
–
–
–
–
Commercial
Industrial
–
–
TYP.
–
–
–
–
–
–
–
95
95
3
64
D
ES
IG
I/O Active Pull-Up Current
Output Short Circuit Current
pL
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
N
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
175
–
V
V
μA
μA
μA
μA
mA
mA
mA
Table 2-0007/2064
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
Operating Power Supply Current
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
U
SE
is
SI
Input or I/O High Leakage Current
20
4
Specifications
ispLSI 2064/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
DESCRIPTION
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
3
1
tsu2 + tco1
-125
–
–
125
7.5
10.0
–
–
–
–
–
–
–
10.0
–
12.0
12.0
7.0
7.0
–
–
–
–
-100
10.0
13.0
–
–
–
–
–
–
-80
15.0
18.5
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
ns
ns
MHz
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
FO
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
100
77.0
111
6.5
–
81.0
57.0
100
9.0
–
0.0
–
N
0.0
–
–
–
–
–
5.0
5.0
Clock Frequency with External Feedback
(
)
S
–
–
–
–
6.5
–
–
8.0
–
17.0
–
18.0
18.0
12.0
12.0
–
–
Select devices have been discontinued.
See Ordering Information section for product status.
100
125
5.0
–
0.0
6.0
–
0.0
–
–
–
–
–
4.0
4.0
5.0
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Product Term OE, Enable
15 Product Term OE, Disable
16 Global OE, Enable
17 Global OE, Disable
EW
N
R
5
U
SE
is
pL
SI
20
64
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
E
D
ES
IG
4.0
5.0
–
–
–
13.5
–
15.0
15.0
9.0
9.0
–
–
0.0
–
8.0
4.5
6.0
0.0
–
6.5
–
–
–
–
4.5
4.5
11.0
10.0
Table 2 - 0030B/2064-130
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