AT25PE20-SSHN-T datasheet, PDF

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AT25PE20-SSHN-T: DescriptionNOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP; Categorystorage storage; File Size2MB，64 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT25PE20-SSHN-T Overview

NOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP

AT25PE20-SSHN-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Adesto Technologies
package instruction	SOP,
Reach Compliance Code	compliant
Factory Lead Time	13 weeks
Other features	IT ALSO OPERATES AT 3V NOMINAL SUPPLY
Maximum clock frequency (fCLK)	70 MHz
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.925 mm
memory density	2097152 bit
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	8
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	1.8 V
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm

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AT25PE20

2-Mbit DataFlash-L

Page Erase Serial Flash Memory

PRELIMINARY DATASHEET

Features



Single 1.65V - 3.6V supply



Serial Peripheral Interface (SPI) compatible



Supports SPI modes 0 and 3



Supports RapidS

™

operation

Continuous read capability through entire array



Up to 85MHz



Low-power read option up to 15MHz



Clock-to-output time (t

) of 6ns maximum

User configurable page size



256 bytes per page (default)



264 bytes per page (customer selectable option)

One SRAM data buffer (256/264 bytes)

Flexible programming options



Byte/Page Program (1 to 256/264 bytes) directly into main memory



Buffer Write



Buffer to Main Memory Page Program



Single Command Page Read-Modify-Write Option

Flexible erase options



Page Erase (256/264 bytes)



Block Erase (2KB)



Sector Erase (32KB)



Chip Erase (2-Mbits)

128-byte Security Register



128 bytes factory programmed with a unique identifier

Hardware and software controlled reset options

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation



300nA Ultra-Deep Power-Down current (typical)



5μA Deep Power-Down current (typical)



25μA Standby current (typical)



7mA Active Read current (typical)

Endurance: 100,000 program/erase cycles per page minimum

Data retention: 20 years

Complies with full industrial temperature range

Green (Pb/Halide-free/RoHS compliant) packaging options



8-lead SOIC (0.150ʺ wide and 0.208" wide)



8-pad Ultra-thin DFN (5 x 6 x 0.6mm)



DS-25PE20–139B–3/2018

Table 1-1.

Pin Configurations

Asserted

State

Symbol

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in the standby mode (not Deep Power-Down

mode) and the output pin (SO) will be in a high-impedance state. When the device is

deselected, data will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device will not enter the standby mode until the completion of

the operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is

always latched on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

Serial Input:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS

is deasserted).

Serial Output:

The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state

whenever the device is deselected (CS is deasserted).

Write Protect:

When the WP pin is asserted, all sectors specified for protection by the Sector

Protection Register will be protected against program and erase operations regardless of

whether the Enable Sector Protection command has been issued or not. The WP pin functions

independently of the software controlled protection method. After the WP pin goes low, the

contents of the Sector Protection Register cannot be modified.

Type

Low

Input

SCK

—

Input

—

Input

—

Output

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle

state once the CS pin has been deasserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected to

whenever possible.

Reset:

A low state on the reset pin (RESET) will terminate the operation in progress and reset

the internal state machine to an idle state. The device will remain in the reset condition as long

as a low level is present on the RESET pin. Normal operation can resume once the RESET pin

is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not utilized, then it is

recommended that the RESET pin be driven high externally.

Low

Input

RESET

Low

Input

GND

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

—

Power

Ground

AT25PE20

DS-25PE20–139B–3/2018

AT25PE20-SSHN-T Related Products

	AT25PE20-SSHN-T	AT25PE20-SHN-T	AT25PE20-MHN-T	AT25PE20-MHN-Y
Description	NOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP	NOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP	NOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP	NOR Flash 2Mb 1.65V-3.6V SPI 85MHz IND TEMP
Maker	Adesto Technologies	Adesto Technologies	Adesto Technologies	Adesto Technologies
Maximum operating temperature	85 °C	+ 85 C	+ 85 C	+ 85 C
Minimum operating temperature	-40 °C	- 40 C	- 40 C	- 40 C
organize	2MX1	256 k x 8	256 k x 8	256 k x 8
Product Category	-	NOR flash memory	NOR flash memory	NOR flash memory
Installation style	-	SMD/SMT	SMD/SMT	SMD/SMT
Package/box	-	SOIC-8	UDFN-8	UDFN-8
series	-	AT25PE20	AT25PE20	AT25PE20
storage	-	2 Mbit	2 Mbit	2 Mbit
maximum clock frequency	-	85 MHz	85 MHz	85 MHz
Interface Type	-	SPI	SPI	SPI
Data bus width	-	8 bit	8 bit	8 bit
Supply voltage - min.	-	1.65 V	1.65 V	1.65 V
Supply voltage - max.	-	3.6 V	3.6 V	3.6 V
Supply current—max.	-	15 mA	15 mA	15 mA
Encapsulation	-	Reel	Reel	Tray
storage type	-	Non-Volatile	Non-Volatile	Non-Volatile
speed	-	85 MHz	85 MHz	85 MHz
Factory packaging quantity	-	2000	6000	570

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