GS81302T07GE-300I datasheet, PDF

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GS81302T07GE-300I: DescriptionStatic random access memory 1.8 or 1.5V 16M x 8 144M; Categorystorage storage; File Size2MB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS81302T07GE-300I Overview

Static random access memory 1.8 or 1.5V 16M x 8 144M

GS81302T07GE-300I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	12 weeks
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	134217728 bit
Memory IC Type	DDR SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS81302T07/10/19/37E-450/400/350/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaDDR

-II+

Burst of 2 SRAM

450 MHz–300 MHz

1.8 V V

1.8 V or 1.5 V I/O

SRAMs. The GS81302T07/10/19/37E SigmaDDR-II+

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Clocking and Addressing Schemes

The GS81302T07/10/19/37E SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 16M x 8 has an 8M

addressable index).

SigmaDDR™ Family Overview

The GS81302T07/10/19/37E are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

Parameter Synopsis

-450

tKHKH

tKHQV

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.03b 8/2017

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81302T07GE-300I Related Products

	GS81302T07GE-300I	GS81302T10E-300I	GS81302T07E-300	GS81302T10GE-300	GS81302T19E-350	GS81302T19GE-300
Description	Static random access memory 1.8 or 1.5V 16M x 8 144M	Static random access memory 1.8 or 1.5V 16M x 9 144M	Static random access memory 1.8 or 1.5V 16M x 8 144M	Static random access memory 1.8 or 1.5V 16M x 9 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M
Is it lead-free?	Lead free	Contains lead	Contains lead	Lead free	Contains lead	Lead free
Is it Rohs certified?	conform to	incompatible	incompatible	conform to	incompatible	conform to
Maker	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,
Contacts	165	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
memory density	134217728 bit	150994944 bit	134217728 bit	150994944 bit	75497472 bit	75497472 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	8	9	8	9	18	18
Number of functions	1	1	1	1	1	1
Number of terminals	165	165	165	165	165	165
word count	16777216 words	16777216 words	16777216 words	16777216 words	4194304 words	4194304 words
character code	16000000	16000000	16000000	16000000	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C
organize	16MX8	16MX9	16MX8	16MX9	4MX18	4MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	NOT SPECIFIED	NOT SPECIFIED	260	NOT SPECIFIED	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
Factory Lead Time	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	-

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