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GS71116AGU-8E

Description
Static Random Access Memory 3.3V 64K x 16 1M E Temp
Categorysemiconductor    Memory IC    Static random access memory   
File Size102KB,13 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
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GS71116AGU-8E Overview

Static Random Access Memory 3.3V 64K x 16 1M E Temp

GS71116AGU-8E Parametric

Parameter NameAttribute value
MakerGSI Technology
Product Categorystatic random access memory
storage1 Mbit
organize64 k x 16
interview time8 ns
Interface TypeParallel
Supply voltage - max.3.6 V
Supply voltage - min.3 V
Supply current—max.-
Minimum operating temperature-
Maximum operating temperature-
Installation styleSMD/SMT
Package/boxBGA-48
seriesGS71116AGU
typeAsynchronous SRAM
Factory packaging quantity270
GS71116AGP/U
TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option:
–40°
to 85°C
• Package line up
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
64K x 16
1Mb Asynchronous SRAM
1
2
3
4
7, 8, 10, 12 ns
3.3 V V
DD
Center V
DD
and V
SS
Fine Pitch BGA 64K x 16-Bump Configuration
5
6
A
B
C
D
E
F
G
H
LB
DQ
16
OE
UB
A
0
A
3
A
5
NC
NC
A
8
A
10
A
13
A
1
A
4
A
6
A
7
NC
A
9
A
11
A
14
A
2
CE
DQ
2
DQ
4
DQ
5
DQ
7
WE
A
15
NC
DQ
1
DQ
3
DQ
14
DQ
15
V
SS
DQ
13
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
NC
A
12
V
DD
V
SS
DQ
6
DQ
8
NC
Description
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in the 6 mm x 8 mm
Fine Pitch BGA and 400 mil TSOP Type-II packages.
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)
Top View
TSOP-II 64K x 16-Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
15
A14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Pin Descriptions
Symbol
A
0
–A
15
DQ
1
–DQ
16
CE
LB
UB
WE
OE
V
DD
V
SS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Top view
44-pin
TSOP II
Package TP
Rev: 1.10 1/2013
1/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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