Data Sheet
FEATURES
12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2.8 GHz VCO
AD9520-0
FUNCTIONAL BLOCK DIAGRAM
CP
LF
OPTIONAL
REFIN
REF1
STATUS
MONITOR
PLL
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.53 GHz to 2.95 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for f
OUT
≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
SWITCHOVER
AND MONITOR
VCO
REFIN
REF2
CLK
DIVIDER
AND MUXES
ZERO
DELAY
LVPECL/
CMOS
DIV/Φ
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
DIV/Φ
DIV/Φ
DIV/Φ
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
The
AD9520-0
serial interface supports both SPI and I²C ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
The
AD9520-0
features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs. If an application requires LVDS
drivers instead of LVPECL drivers, refer to the
AD9522-0.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The
AD9520-0
is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage of up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The
AD9520-0
is specified for operation over the standard
industrial range of −40°C to +85°C.
GENERAL DESCRIPTION
The
AD9520-0
1
provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz
to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
1
AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when
AD9520-0
is used, it refers to that specific member of the
AD9520 family.
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07213-001
SPI/I
2
C CONTROL
PORT AND
DIGITAL LOGIC
EEPROM
AD9520
AD9520-0
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 7
Clock Outputs ............................................................................... 7
Timing Characteristics ................................................................ 8
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) ............................................................ 10
Clock Output Absolute Phase Noise (Internal VCO Used) .. 11
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO) .................................................................. 11
Clock Output Absolute Time Jitter (Clock Cleanup
Using Internal VCO) .................................................................. 11
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) .............................................................. 12
Clock Output Additive Time Jitter
(VCO Divider Not Used)........................................................... 12
Clock Output Additive Time Jitter (VCO Divider Used) ..... 12
Serial Control Port—SPI Mode ................................................ 13
Serial Control Port—I²C Mode ................................................ 14
PD, EEPROM, RESET, and SYNC Pins .................................. 15
Serial Port Setup Pins—SP1, SP0 ............................................. 15
LD, STATUS, and REFMON Pins ............................................ 15
Power Dissipation ....................................................................... 16
Absolute Maximum Ratings .......................................................... 17
Thermal Resistance .................................................................... 17
ESD Caution ................................................................................ 17
Data Sheet
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 26
Detailed Block Diagram ................................................................ 27
Theory of Operation ...................................................................... 28
Operational Configurations ...................................................... 28
Zero Delay Operation ................................................................ 42
Clock Distribution ..................................................................... 43
Reset Modes ................................................................................ 49
Power-Down Modes .................................................................. 50
Serial Control Port ......................................................................... 51
SPI/I²C Port Selection................................................................ 51
I²C Serial Port Operation .......................................................... 51
SPI Serial Port Operation .......................................................... 54
SPI Instruction Word (16 Bits) ................................................. 55
SPI MSB/LSB First Transfers .................................................... 55
EEPROM Operations ..................................................................... 58
Writing to the EEPROM ........................................................... 58
Reading from the EEPROM ..................................................... 58
Programming the EEPROM Buffer Segment ......................... 59
Thermal Performance .................................................................... 60
Register Map ................................................................................... 61
Register Map Descriptions ............................................................ 64
Applications Information .............................................................. 77
Frequency Planning Using the AD9520 .................................. 77
Using the AD9520 Outputs for ADC Clock Applications .... 77
LVPECL Clock Distribution ..................................................... 78
CMOS Clock Distribution ........................................................ 78
Outline Dimensions ....................................................................... 80
Ordering Guide .......................................................................... 80
Rev. B | Page 2 of 80
Data Sheet
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changed AD9520 to AD9520-0 .................................. Throughout
Change to PD Power-Down, Maximum Sleep Parameter,
Table 18 .............................................................................................16
Updated Outline Dimensions ........................................................80
8/2013—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
General Description Section ............................................................ 1
Changes to Table 2 ............................................................................ 4
Changes to Input Frequency Parameter; Change to Input
Sensitivity, Differential Parameter Test Conditions/Comments,
Table 3 ................................................................................................. 7
Change to Output Differential Voltage, V
OD
Parameter Test
Conditions/Comments; Added Source Current and Sink
Current Parameters, Table 4 ............................................................ 7
Reordered Figure 2 to Figure 4 ........................................................ 9
Change to Reset Timing, Pulse Width Low Parameter, Table 15 ...15
Change to PLL Locked; One LVPECL Output Enabled
Parameter, f
OUT
Value in Test Conditions/Comments, Table 18 ..16
Change to Junction Temperature, Table 19; Reformatted
Table 19 .....................................................................................................17
Change to Pin 4, Pin 10, and Pin 22 Descriptions, Table 21 .....18
Deleted Figure 13, Renumbered Sequentially .............................22
Reordered Figure 31 and Figure 32; Moved Figure 34 and
Figure 35 to PLL External Loop Filter Section, Page 35;
Added Figure 33, Renumbered Sequentially ...............................25
Change to Mode 0—Internal VCO and Clock Distribution
Section ..............................................................................................28
Change to Configuration of the PLL Section; Changes to
Charge Pump (CP) Section ............................................................34
Changes to On-Chip VCO Section and PLL External Loop
Filter Section; Added Figure 40; Moved Figure 41 and Figure 42
from Typical Performance Characteristics Section to PLL
External Loop Filter Section; Changes to PLL Reference
Inputs Section ..................................................................................35
Changes to Reference Switchover Section ...................................36
Change to Prescaler Section and A and B Counters Section;
Changes to Table 29 ........................................................................37
Changes to Current Source Digital Lock Detect (CSDLD)
Section ..............................................................................................38
AD9520-0
Changes to Frequency Status Monitors Section and VCO
Calibration Section ......................................................................... 41
Added Table 31, Renumbered Sequentially; Change to
Internal Zero Delay Mode Section ............................................... 42
Changes to External Zero Delay Mode Section .......................... 43
Change to Clock Frequency Division Section; Added Channel
Divider Maximum Frequency Section ......................................... 45
Reformatted Table 36 to Table 39.................................................. 46
Change to Phase Offset or Coarse Time Delay Section ............. 47
Change to LVPECL Output Drivers Section; Changes to CMOS
Output Drivers Section .................................................................. 49
Changes to Soft Reset via the Serial Port Section and Soft
Reset to Settings in EEPROM When EEPROM Pin = 0b
via the Serial Port Section .............................................................. 50
Change to Pin Descriptions Section, SPI Mode Operation
Section, and Write Section ............................................................. 54
Changes to SPI Instruction Word (16 Bits) Section ................... 55
Changes to EEPROM Operations Section, Writing to the
EEPROM Section, and Reading from the EEPROM Section ... 58
Changes to Programming the EEPROM Buffer Segment
Section and Register Section Definition Group Section;
Added Operational Codes Section Heading ............................... 59
Changes to Table 50 ........................................................................ 61
Added Unused Bits to Register Map Descriptions Section;
Changes to Address 0x000, Bit 5, and Added Address 0x003,
Table 51; Changes to Address 0x000, Bit 5, and Added
Address 0x003, Table 52 ................................................................. 64
Changes to Address 0x017, Table 54 ............................................ 66
Changes to Address 0x018, Bit 4 and Bits[2:1], Table 54 ........... 67
Changes to Address 0x01B, Bits[4:0], Table 54 ........................... 69
Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,
Table 56 ............................................................................................. 72
Changes to Address 0x197, Bit 5, Table 56 .................................. 73
Changes to Address 0x19A, Bit 5, Table 56 ................................. 74
Changes to Table 60 ........................................................................ 75
Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,
Table 61 ............................................................................................. 76
Change to Frequency Planning Using the AD9520 Section ..... 77
Added LVPECL Y-Termination and Far-End Thevenin
Termination Headings; Changes to CMOS Clock Distribution
Section ....................................................................................................... 78
9/2008—Revision 0: Initial Version
Rev. B | Page 3 of 80
AD9520-0
SPECIFICATIONS
Data Sheet
Typical is given for V
S
= V
S_DRV
= 3.3 V ± 5%; V
S
≤ V
CP
≤ 5.25 V; T
A
= 25°C; RSET = 4.12 kΩ; CP
RSET
= 5.1 kΩ, unless otherwise noted. Minimum
and maximum values are given over full V
S
and T
A
(−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
POWER PINS
VS
VS_DRV
VCP
CURRENT SET RESISTORS
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
V
S
Typ
3.3
Max
3.465
V
S
5.25
Unit
V
V
V
kΩ
kΩ
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA
(CP_lsb = 600 µA); actual current can be calculated
by CP_lsb = 3.06/CP
RSET
; connect to ground
Bypass for internal LDO regulator;
necessary for LDO stability; connect to ground
4.12
5.1
BYPASS PIN CAPACITOR
220
nF
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON CHIP)
Frequency Range
VCO Gain (K
VCO
)
Tuning Voltage (V
T
)
Frequency Pushing (Open-Loop)
Phase Noise at 1 kHz Offset
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled with
DC Offset Off)
Input Frequency (AC-Coupled with
DC Offset On)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled with
DC Offset Off)
Input Sensitivity (AC-Coupled with
DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
1.35
1.30
4.0
4.4
10
Min
2530
52
0.5
1
−51
−108
−127
V
CP
− 0.5
Typ
Max
2950
Unit
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
See Figure 8
V
T
≤ V
S
when using internal VCO
f = 2550 MHz
f = 2550 MHz
f = 2550 MHz
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match V
CM
(self-bias voltage)
PLL figure of merit (FOM) increases with increasing
slew rate (see Figure 12); the input sensitivity is
sufficient for ac-coupled LVDS and LVPECL signals
Self-bias voltage of REFIN
1
Self-bias voltage of REFIN
1
Self-biased
1
Self-biased
1
Two single-ended CMOS-compatible inputs
Slew rate must be >50 V/µs
Slew rate must be >50 V/µs, and input amplitude
sensitivity specification must be met; see the input
sensitivity parameter
Slew rate > 50 V/µs; CMOS levels
V
IH
should not exceed V
S
V
IH
should not exceed V
S
0
280
1.60
1.50
4.8
5.3
250
MHz
mV p-p
1.75
1.60
5.9
6.4
250
250
V
V
kΩ
kΩ
MHz
MHz
MHz
V p-p
V p-p
V
V
µA
pF
0
0.55
1.5
2.0
−100
2
250
3.28
2.78
0.8
+100
Rev. B | Page 4 of 80
Each pin, REFIN (REF1)/REFIN (REF2)
Data Sheet
Parameter
Pulse Width High/Low
Crystal Oscillator
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Reference Input Clock Doubler Frequency
Antibacklash Pulse Width
Min
1.8
Typ
Max
Unit
ns
AD9520-0
Test Conditions/Comments
The amount of time that a square wave is high/low;
determines the allowable input duty cycle
16.62
33.33
30
100
45
50
1.3
2.9
6.0
MHz
Ω
MHz
MHz
MHz
ns
ns
ns
Antibacklash pulse width = 1.3 ns
Antibacklash pulse width = 2.9 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
CP
V
is the CP pin voltage; V
CP
is the charge pump
power supply voltage (VCP pin)
Programmable
With CP
RSET
= 5.1 kΩ; higher I
CP
is possible by changing
CP
RSET
With CP
RSET
= 5.1 kΩ; lower I
CP
is possible by changing
CP
RSET
CP
V
= V
CP
/2
0.004
CHARGE PUMP (CP)
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
CP
RSET
Range
I
CP
High Impedance Mode Leakage
Sink-and-Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL N DIVIDER DELAY
000
001
010
011
100
101
110
111
PLL R DIVIDER DELAY
000
001
010
011
100
101
110
111
4.8
0.60
2.5
2.7
1
1
1.5
2
10
mA
mA
%
kΩ
nA
%
%
%
0.5 V < CP
V
< V
CP
− 0.5 V; CP
V
is the CP pin voltage;
V
CP
is the charge pump power supply voltage (VCP pin)
0.5 V < CP
V
< V
CP
− 0.5 V
CP
V
= V
CP
/2
300
600
900
200
1000
2400
3000
3000
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
A, B counter input frequency (prescaler input
frequency divided by P)
Register 0x019[2:0]; see Table 54
Off
385
486
623
730
852
976
1101
Off
365
486
608
730
852
976
1101
Rev. B | Page 5 of 80
ps
ps
ps
ps
ps
ps
ps
Register 0x019[5:3]; see Table 54
ps
ps
ps
ps
ps
ps
ps
MCU
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