GLS29EE512 Small-Sector Flash™
512 Kbit (64K x8) Page-Write EEPROM
Datasheet 11.000
July 2018
Features
•
Single Voltage Read and Write Operations
- 4.5-5.5V for GLS29EE512
•
Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
•
Low Power Consumption
- Active Current: 20 mA (typical)
- Standby Current: 10 µA (typical)
•
Fast Page-Write Operation
- 128 Bytes per Page, 512 Pages
- Page-Write Cycle: 5 ms (typical)
- Complete Memory Rewrite: 2.5 sec (typical)
- Effective Byte-Write Cycle Time: 39 µS (typical)
•
Fast Read Access Time
- 4.5-5.5V operation: 70 ns
•
Latched Address and Data
•
Automatic Write Timing
- Internal V
PP
Generation
•
End of Write Detection
- Toggle Bit
- Data# Polling
•
Hardware and Software Data Protection
•
Product Identification can be accessed via
Software Operation
•
TLL I/O Compatibility
•
JEDEC Standard
- Flash EEPROM Pinouts and Command Sets
•
Packages Available
- 32-lead PLCC
- 32-lead TSOP (8mm x 20mm)
•
All Devices are RoHS Compliant
Product Description
GLS29EE512 Small-Sector Flash™ is a 64K x8
CMOS, Page-Write EEPROM manufactured with high-
performance SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches. GLS29EE512 writes with a
single power supply. Internal Erase/Program is
transparent to the user. GLS29EE512 conforms to
JEDEC standard pin assignments for byte-wide
memories.
Featuring
high
performance
Page-Write,
GLS29EE512 provides a typical Byte-Write time of 39
μsec.
The entire memory, i.e., 64 KByte, can be
written page-by-page in as little as 2.5 seconds, when
using interface features such as Toggle Bit or Data#
Polling to indicate the completion of a Write cycle. To
protect against inadvertent write, GLS29EE512 have
on-chip hardware and Software Data Protection
schemes. Designed, manufactured and tested for a
wide spectrum of applications, GLS29EE512 is
offered with a guaranteed Page-Write endurance of
10,000 cycles. Data retention is rated at greater than
100 years.
GLS29EE512 is suited for applications that require
convenient and economical updating of program,
configuration, or data memory. For all system
applications, GLS29EE512 significantly improves
performance and reliability, while lowering power
consumption. GLS29EE512 improves flexibility while
lowering the cost for program, data, and configuration
storage applications.
To meet high density, surface mount requirements,
GLS29EE512 is offered in 32-lead PLCC and 32-lead
TSOP packages. See Figures 1 and 2 for pin
assignments.
Device Operation
The Greenliant Page-Write EEPROM offers in-circuit
electrical write capability. GLS29EE512 does not
require separate Erase and Program operations. The
internally timed Write cycle executes both erase and
program transparently to the user. GLS29EE512 has
industry standard optional Software Data Protection,
which Greenliant recommends always to be enabled.
GLS29EE512 is compatible with industry standard
EEPROM pinouts and functionality.
These specifications are subject to change without notice.
© 2018 Greenliant
GLS FS0019 Rev. 01
1
07/26/2018
S71060
GLS29EE512 Small-Sector Flash™
512 Kbit (64K x8) Page-Write EEPROM
Datasheet 11.000
July 2018
Read
The Read operations of GLS29EE512 is controlled by
CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read Cycle
Timing diagram for further details (Figure 3).
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page-
load cycle, and the internal Write cycle. The Software
Data Protection consists of a specific three-byte load
sequence that allows writing to the selected page and
will leave GLS29EE512 protected at the end of the
Page-Write. The page-load cycle consists of loading 1
to 128 Bytes of data into the page buffer. The internal
Write cycle consists of the T
BLCO
time-out and the
write timer operation. During the Write operation, the
only valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to
128 Bytes of data into the page buffer of
GLS29EE512 before the initiation of the internal Write
cycle. During the internal Write cycle, all the data in
the page buffer is written simultaneously into the
memory array. Hence, the Page-Write feature of
GLS29EE512 allows the entire memory to be written
in as little as 2.5 seconds. During the internal Write
cycle, the host is free to perform additional tasks, such
as to fetch data from other locations in the system to
set up the write to the next page. In each Page-Write
operation, all the bytes that are loaded into the page
buffer must have the same page address, i.e. A
7
through A
16
. Any byte not loaded with user data will
be written to FFH.
See Figures 4 and 5 for the Page-Write cycle timing
diagrams. If after the completion of the three-byte
SDP load sequence or the initial byte-load cycle, the
host loads a second byte into the page buffer within a
byte-load cycle time (T
BLC
) of 100 μs,
GLS29EE512
will stay in the page-load cycle. Additional bytes are
then loaded consecutively. The page-load cycle will
be terminated if no additional byte is loaded into the
page buffer within 200 μs
(T
BLCO
) from the last byte-
load cycle, i.e., no subsequent WE# or CE# high-to-
low transition after the last rising edge of WE# or CE#.
Data in the page buffer can be changed by a
subsequent byte-load cycle. The page-load period can
continue indefinitely, as long as the host continues to
load the device within the byte-load cycle time of 100
μs. The
page to be loaded is determined by the page
address of the last byte loaded.
Write
The Page-Write to GLS29EE512 should always use
the JEDEC Standard Software Data Protection (SDP)
three-byte
command
sequence.
GLS29EE512
contains the optional JEDEC approved Software Data
Protection scheme. Greenliant recommends that SDP
always be enabled, thus, the description of the Write
operations will be given using the SDP enabled
format.
The three-byte SDP Enable and SDP Write
commands are identical; therefore, any time a SDP
Write command is issued, Software Data
Protection is automatically assured.
The first time
the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the
same command bypasses the data protection for the
page being written. At the end of the desired Page-
Write, the entire device remains protected. For
additional descriptions, please see the application
note,
Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories.
The Write operation consists of three steps. Step 1 is
the three-byte load sequence for Software Data
Protection. Step 2 is the byte-load cycle to a page
buffer of GLS29EE512. Steps 1 and 2 use the same
timing for both operations. Step 3 is an internally
controlled Write cycle for writing the data loaded in the
page buffer into the memory array for nonvolatile
storage.
During both the SDP three-byte load sequence and
the byte-load cycle, the addresses are latched by the
falling edge of either CE# or WE#, whichever occurs
last. The data is latched by the rising edge of either
CE# or WE#, whichever occurs first. The internal
Write cycle is initiated by the T
BLCO
timer after the
rising edge of WE# or CE#, whichever occurs first.
The Write cycle, once initiated, will continue to
completion, typically within 5 ms. See Figures 4 and 5
for WE# and CE# controlled Page-Write cycle timing
diagrams and Figures 15 and 17 for flowcharts.
Software Chip-Erase
GLS29EE512 provides a Chip-Erase operation, which
allows the user to simultaneously clear the entire
memory array to the “1” state. This is useful when the
entire device must be quickly erased.
The Software Chip-Erase operation is initiated by
using a specific six-byte load sequence. After the load
sequence, the device enters into an internally timed
These specifications are subject to change without notice.
© 2018 Greenliant
GLS FS0019 Rev. 01
2
07/26/2018
S71060
GLS29EE512 Small-Sector Flash™
512 Kbit (64K x8) Page-Write EEPROM
Datasheet 11.000
July 2018
cycle similar to the Write cycle. During the Erase
operation, the only valid read is Toggle Bit. See Table
4 for the load sequence, Figure 9 for timing diagram,
and Figure 18 for the flowchart.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less
than 5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or
WE# high will inhibit the Write operation. This
prevents inadvertent writes during power-up or power-
down.
Write Operation Status Detection
GLS29EE512 provides two software means to detect
the completion of a Write cycle, in order to optimize
the system Write cycle time. The software detection
includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The end of write detection mode is
enabled after the rising WE# or CE# whichever occurs
first, which initiates the internal Write cycle.
The actual completion of the nonvolatile write is
asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous
with the completion of the Write cycle. If this occurs,
the system may possibly get an erroneous result, i.e.,
valid data may appear to conflict with either DQ
7
or
DQ
6
. In order to prevent spurious rejection, if an
erroneous result occurs, the software routine should
include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then
the device has completed the Write cycle, otherwise
the rejection is valid.
Software Data Protection (SDP)
GLS29EE512 provides the JEDEC approved optional
Software Data Protection scheme for all data
alteration operations, i.e., Write and Chip-Erase. With
this scheme, any Write operation requires the
inclusion of a series of three byte-load operations to
precede the data loading operation. The three-byte
load sequence is used to initiate the Write cycle,
providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or
power-down. The GLS29EE512 is shipped with the
Software Data Protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will
then be automatically set into the data protect mode.
Any subsequent Write operation will require the
preceding three-byte sequence. See Table 4 for the
specific software command codes and Figures 4 and
5 for the timing diagrams. To set the device into the
unprotected mode, a six-byte sequence is required.
See Table 4 for the specific codes and Figure 8 for the
timing diagram. If a Write is attempted while SDP is
enabled the device will be in a non-accessible state
for ~ 300
μs. Greenliant recommends Software Data
Protection always be enabled. See Figure 16 for
flowcharts.
GLS29EE512 Software Data Protection is a global
command, protecting (or unprotecting) all pages in the
entire memory array once enabled (or disabled).
Therefore, using SDP for a single Page-Write will
enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled or disabled,
although the page addressed during the SDP write will
be written.
Single power supply reprogrammable nonvolatile
memories may be unintentionally altered. Greenliant
strongly recommends that Software Data Protection
(SDP) always be enabled. GLS29EE512 should be
programmed using the SDP command sequence.
Greenliant recommends the SDP Disable Command
Sequence not be issued to the device prior to writing.
07/26/2018
S71060
Data# Polling (DQ
7
)
When GLS29EE512 is in the internal Write cycle, any
attempt to read DQ
7
of the last byte loaded during the
byte-load cycle will receive the complement of the true
data. Once the Write cycle is completed, DQ
7
will
show true data. Note that even though DQ
7
may have
valid data immediately following the completion of an
internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus
will appear in subsequent successive Read cycles
after an interval of 1
μs. See Figure
6 for Data#
Polling timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating ‘0’s and
‘1’s, i.e., toggling between 0 and 1. When the Write
cycle is completed, the toggling will stop. The device
is then ready for the next operation. See Figure 7 for
Toggle Bit timing diagram and Figure 15 for a
flowchart. The initial read of the Toggle Bit will
typically be a “1”.
Data Protection
GLS29EE512 provide both hardware and software
features to protect nonvolatile data from inadvertent
writes.
These specifications are subject to change without notice.
© 2018 Greenliant
GLS FS0019 Rev. 01
3
GLS29EE512 Small-Sector Flash™
512 Kbit (64K x8) Page-Write EEPROM
Datasheet 11.000
July 2018
Please refer to the following application note for more
information on using SDP,
Protecting Against
Unintentional Writes When Using Single Power
Supply Flash Memories.
Product Identification Mode Exit
In order to return to the standard Read mode, the
Software Product Identification mode must be exited.
Exiting is accomplished by issuing the Software ID
Exit (reset) operation, which returns the device to the
Read operation. The Reset operation may also be
used to reset the device to the Read mode after an
inadvertent transient condition that apparently causes
the device to behave abnormally, e.g., not read
correctly. See Table 4 for software command codes,
Figure 11 for timing waveform, and Figure 17 for a
flowchart.
Product Identification
The Product Identification mode identifies the device
as GLS29EE512 and manufacturer as Greenliant.
This mode is accessed via software. For details, see
Table 4, Figure 10 for the software ID entry, and Read
timing diagram and Figure 17 for the ID entry
command sequence flowchart.
Table 1: Product Identification
Address
Manufacturer’s ID
Device ID
GLS29EE512
0000H BFH
0001H 5DH
Data
0000H BFH
0001H 5DH
These specifications are subject to change without notice.
© 2018 Greenliant
GLS FS0019 Rev. 01
4
07/26/2018
S71060
GLS29EE512 Small-Sector Flash™
512 Kbit (64K x8) Page-Write EEPROM
Datasheet 11.000
July 2018
Figure 1: Pin Assignment for 32-Lead PLCC
Figure 2: Pin Assignment for 32-Lead TSOP
Table 2: Pin Description
These specifications are subject to change without notice.
© 2018 Greenliant
GLS FS0019 Rev. 01
5
07/26/2018
S71060
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