GS81280Z18/36GT-400/333/250/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 100-lead TQFP package available
144Mb Pipelined and Flow Through
Synchronous NBT SRAM
400 MHz–200 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS81280Z18/36GT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS81280Z18/36GT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Functional Description
The GS81280Z18/36GT is a 144Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-400
2.5
2.5
610
690
4.0
4.0
430
470
-333
2.5
3.0
530
600
4.5
4.5
400
435
-250
2.5
4.0
430
470
5.5
5.5
360
380
-200
3.0
5.0
360
400
6.5
6.5
295
330
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Rev: 1.01b 8/2017
1/22
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81280Z18/36GT-400/333/250/200
TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
DQ
A
DQ
B
DQ
C
DQ
D
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
NU
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
In
In
In
In
In
In
—
—
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
No Connect
Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may
be left unconnected, tied Low (to V
SS
), or tied High (to V
DDQ
or V
DD
).
Rev: 1.01b 8/2017
4/22
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADI Reference Circuit
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