IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC
IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT SRAM
APRIL 2017
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-
ball BGA packages
Power supply:
LPS: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
VPS: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
JTAG Boundary Scan for BGA packages
Industrial and Automotive temperature support
Lead-free available
Error Detection and Error Correction
DESCRIPTION
The 4Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and
networking applications. The
IS61(64)LPS/VPS12836EC
are
organized as
131,072
words by 36bits. The
IS61(64)LPS/VPS12832EC
are organized as
131,072
words by
32bits. The
IS61(64)LPS/VPS25618EC
are organized as
262,144
words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (/BWE) input combined with one or more
individual byte write signals (/BWx). In addition, Global
Write (/GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address Status
Processor) or /ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the /ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
f
MAX
Parameter
Clock Access Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D2
04/14/2017
1
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC
IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC
PIN CONFIGURATION
128K x 36, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Burst Address
Advance
Synchronous Address Status
Processor
Synchronous Address Status
Controller
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
JTAG Pins
Asynchronous Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
3
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
TCK,TDI,TDO,TM
S
ZZ
NC
VDD
VDDQ
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D2
04/14/2017
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC
IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC
VSS
Ground
128K x 32, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
TCK,TDI,TDO,TMS
ZZ
NC
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Burst Address Advance
Synchronous Address Status
Processor
Synchronous Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
JTAG Pins
Asynchronous Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D2
04/14/2017
VDD
VDDQ
VSS
4
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC
IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC
256K x 18, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
DQPx
TCK,TDI,TDO,TM
S
ZZ
NC
VDD
VDDQ
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Burst Address
Advance
Synchronous Address Status
Processor
Synchronous Address Status
Controller
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Synchronous Global Write Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
JTAG Pins
Asynchronous Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D2
04/14/2017
5
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