S25FS128S
S25FS256S
1.8 V, Serial Peripheral Interface
with Multi-I/O, MirrorBit
®
Non-Volatile Flash
Features
Density
– S25FS128S-128 Mbits (16 Mbytes)
– S25FS256S-256 Mbits (32 Mbytes)
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command subset and footprint compatible with
S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
– Multi I/O Command subset and footprint compatible with
S25FL-P, and S25FL-S SPI families
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad
I/O
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) and
Common Flash Interface (CFI), for configuration
information
Program
– 256- or 512-byte Page Programming buffer
– Program suspend and resume
– Automatic ECC – internal hardware Error Correction Code
generation with single-bit error correction
Erase
– Hybrid sector option
– Physical set of eight 4-kbyte sectors and one 32-kbyte
sector at the top or bottom of address space with all
remaining sectors of 64 kbytes
– Uniform sector option
– Uniform 64-kbyte or 256-kbyte blocks for software
compatibility with higher density and future devices
– Erase suspend and resume
– Erase status evaluation
– 100,000 Program-Erase Cycles, minimum
– 20 Year Data Retention, minimum
Security Features
– One-Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
– Option for password control of read access
Technology
– Cypress 65 nm MirrorBit
®
Technology with Eclipse
™
Architecture
Supply Voltage
– 1.7V to 2.0V
Temperature Range / Grade
– Industrial (-40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Automotive AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive AEC-Q100 Grade 1 (–40°C to +125°C)
Packages (All Pb-Free)
– 8-lead SOIC 208 mil (SOC008) — FS128S only
– WSON 6
5 mm (WND008) — FS128S only
– WSON 6
8 mm (WNH008)
– 16-lead SOIC 300 mil (SO3016 — FS256S only)
– BGA-24 6
8 mm
– 5
5 ball (FAB024) footprint
– 4
6 ball (FAC024) footprint
– Known Good Die, and Known Tested Die
Cypress Semiconductor Corporation
Document Number: 002-00368 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 11, 2018
S25FS128S
S25FS256S
Performance Summary
Table 1. Maximum Read Rates
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
133
133
133
Mbytes/s
6.25
16.5
33
66
Table 2. Maximum Read Rates DDR
Command
DDR Quad I/O Read
Clock Rate (MHz)
80
Mbytes/s
80
Table 3. Typical Program and Erase Rates
Operation
Page Programming (256-bytes Page Buffer)
Page Programming (512-bytes Page Buffer)
4-kbyte Physical Sector Erase (Hybrid Sector Option)
64-kbyte Physical Sector Erase (Hybrid Sector Option)
256-kbyte Sector Erase (Uniform Logical Sector Option)
712
1080
16
275
275
kbytes/s
Table 4. Typical Current Consumption (–40°C to +85°C)
Operation
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 133 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Deep Power-Down
10
20
60
70
60
60
0.025
0.006
Current (mA)
Document Number: 002-00368 Rev. *K
Page 2 of 153
S25FS128S
S25FS256S
Contents
Performance Summary
........................................................ 2
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.3
7.4
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
5
7
8
7.5
7.6
8.
8.1
8.2
8.3
8.4
8.5
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
10.
11.
11.1
11.2
11.3
OTP Address Space ..................................................... 52
Registers....................................................................... 53
Data Protection
........................................................... 70
Secure Silicon Region (OTP)........................................ 70
Write Enable Command................................................ 70
Block Protection ............................................................ 71
Advanced Sector Protection ......................................... 72
Recommended Protection Process .............................. 77
Commands
.................................................................. 78
Command Set Summary............................................... 79
Identification Commands .............................................. 84
Register Access Commands......................................... 86
Read Memory Array Commands .................................. 97
Program Flash Array Commands ............................... 104
Erase Flash Array Commands.................................... 106
One-Time Program Array Commands ........................ 113
Advanced Sector Protection Commands .................... 114
Reset Commands ....................................................... 120
DPD Commands ......................................................... 122
Embedded Algorithm Performance Tables.............
124
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Multiple Input / Output (MIO)........................................ 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 10
Serial Output (SO) / IO1............................................... 10
Write Protect (WP#) / IO2 ............................................ 10
IO3 / RESET# ............................................................. 11
Voltage Supply (VCC).................................................. 11
Supply and Signal Ground (V
SS
) ................................. 11
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 12
Block Diagrams............................................................ 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Latch-Up Characteristics..............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Physical Interface
......................................................
SOIC 16-Lead Package ...............................................
8-Connector Packages ................................................
FAB024 24-Ball BGA Package ....................................
FAC024 24-Ball BGA Package ....................................
14
14
15
19
22
22
23
23
23
24
24
25
27
29
29
29
30
33
36
38
38
40
44
46
Data Integrity
............................................................. 125
Erase Endurance ........................................................ 125
Data Retention ............................................................ 125
Serial Flash Discoverable Parameters (SFDP) Address
Map............................................................................. 125
11.4 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 128
11.5 Initial Delivery State .................................................... 146
12.
13.
Ordering Part Number
.............................................. 147
Contact
...................................................................... 149
Address Space Maps.................................................
48
Overview ...................................................................... 48
Flash Memory Array..................................................... 48
ID-CFI Address Space ................................................. 51
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space.............................................................. 51
Document Number: 002-00368 Rev. *K
Page 3 of 153
S25FS128S
S25FS256S
1.
1.1
Overview
General Description
The Cypress S25FS-S family devices are flash non-volatile memory products using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
TheS25FS-S family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and
output (Single I/O or SIO) is supported as well as optional 2-bit (Dual I/O or DIO) and 4-bit wide Quad I/O (QIO) or Quad Peripheral
Interface (QPI) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate
(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS-S family devices at the higher
clock rates supported, with Quad or DDR Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR flash memories, while reducing signal count dramatically.
The S25FS-S family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
Document Number: 002-00368 Rev. *K
Page 4 of 153
S25FS128S
S25FS256S
1.2
1.2.1
Migration Notes
Features Comparison
The S25FS-S family is command subset and footprint compatible with prior generation FL-S, FL-K, and FL-P families. However, the
power supply and interface voltages are nominal 1.8 V.
Table 5. Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Rate (typ.)
Page Programming Rate
(typ.)
OTP
Advanced Sector
Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Deep Power-Down
Operating Temperature
FS-S
65 nm
MirrorBit Eclipse
128 Mb, 256 Mb
x1, x2, x4
1.7 V–2.0 V
6 MB/s (50 MHz)
16.5 MB/s (133 MHz)
33 MB/s (133 MHz)
66 MB/s (133 MHz)
80 MB/s (80 MHz)
256B / 512B
64 kB / 256 kB
4 kB (option)
500 kB/s
0.71 MB/s (256B)
1.08 MB/s (512B)
1024B
Yes
No
Yes
Yes
Yes
FL-S
65 nm
MirrorBit Eclipse
128 Mb, 256 Mb, 512 Mb, 1
Gb
x1, x2, x4
2.7 V–3.6 V / 1.65 V–3.6 V
V
IO
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
80 MB/s (80 MHz)
256B / 512B
64 kB / 256 kB
4 kB (option)
500 kB/s
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
Yes
Yes
Yes
Yes
No
256B
4 kB / 32 kB / 64 kB
4 kB
136 kB/s (4 kB)
437 kB/s (64 kB)
365 kB/s
768B (3x256B)
No
No
Yes
Yes
Yes
–40 °C to +85 °C
256B
64 kB / 256 kB
4 kB
130 kB/s
170 kB/s
506B
No
No
No
No
Yes
–40 °C to +85 °C / +105 °C
FL-K
90 nm
Floating Gate
4 Mb - 128 Mb
x1, x2, x4
2.7 V–3.6 V
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
FL-P
90 nm
MirrorBit
32 Mb - 256 Mb
x1, x2, x4
2.7 V–3.6 V
6 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
–40 °C to +85 °C / +105 °C
–40 °C to +85 °C / +105 °C
/ +125 °C
Notes:
1. The 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. The FL-P column indicates FL129P MIO SPI device (for 128-Mb density), FL128P does not support MIO, OTP, or 4-kB sectors.
3. 64-kB Sector Erase option only for 128-Mb/256-Mb density FL-P, FL-S and FS-S devices.
4. The FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. 512-Mb/1-Gb FL-S devices support 256-kB sector only.
6. Only 128-Mb/256-Mb density FL-S devices have 4-kB parameter sector option.
7. Refer to individual data sheets for further details.
Document Number: 002-00368 Rev. *K
Page 5 of 153
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