AT25PE16-SHF-B datasheet, PDF - EEWORLD Datasheet

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AT25PE16-SHF-B: DescriptionNOR Flash 16Mb 1.65V-3.6V SPI 85MHz IND TEMP; Categorysemiconductor Memory IC NOR flash memory; File Size1MB，63 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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NOR Flash 16Mb 1.65V-3.6V SPI 85MHz IND TEMP

AT25PE16-SHF-B Parametric

Parameter Name	Attribute value
Maker	Adesto Technologies
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	SOIC-8
series	AT25PE16
storage	16 Mbit
maximum clock frequency	85 MHz
Interface Type	SPI
organize	2 M x 8
Data bus width	8 bit
Supply voltage - min.	2.3 V
Supply voltage - max.	3.6 V
Supply current—max.	22 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Encapsulation	Tube
storage type	NOR
speed	85 MHz
type	No Boot Block
standard	Not Supported
Factory packaging quantity	90

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AT25PE16

16-Mbit DataFlash-L

Page Erase Serial Flash Memory

DATASHEET

Features

Single 2.3V - 3.6V supply

Serial Peripheral Interface (SPI) compatible

Supports SPI modes 0 and 3

Supports RapidS

™

operation

Continuous read capability through entire array

Up to 85MHz

Low-power read option up to 15MHz

Clock-to-output time (t

) of 6ns maximum

User configurable page size

512 bytes per page (default)

528 bytes per page (customer selectable option)

Two fully independent SRAM data buffers (512/528 bytes)

Allows receiving data while reprogramming the main memory array

Flexible programming options

Byte/Page Program (1 to 512/528 bytes) directly into main memory

Buffer Write

Buffer to Main Memory Page Program

Flexible erase options

Page Erase (512/528 bytes)

Block Erase (4KB)

Sector Erase (128KB)

Chip Erase (16-Mbits)

128-byte Security Register

128 bytes factory programmed with a unique identifier

Hardware and software controlled reset options

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation

300nA Ultra-Deep Power-Down current (typical)

5µA Deep Power-Down current (typical)

25µA Standby current (typical)

7mA Active Read current (typical)

Endurance: 100,000 program/erase cycles per page minimum

Data retention: 20 years

Complies with full industrial temperature range

Green (Pb/Halide-free/RoHS compliant) packaging options

8-lead SOIC (0.150" wide and 0.208" wide)

8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

DS-25PE16-143C–8/2018

Description

The Adesto

AT25PE16 is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for a

wide variety of digital voice, image, program code, and data storage applications. The AT25PE16 also supports the

RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized

as 4,096 pages of 512 bytes (default) or 528 bytes (customer option) each. In addition to the main memory, the

AT25PE16 also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in

the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability

to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory,

and E

PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write

operation.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the

Adesto DataFlash-L

uses a serial interface to sequentially access its data. The simple sequential access dramatically

reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,

and reduces package size. The device is optimized for use in many commercial and industrial applications where

high-density, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT25PE16 does not require high input voltages for programming.

The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program and read

operations. The AT25PE16 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

Pin Configurations and Pinouts

Figure 1-1. Pinouts

8-lead SOIC

Top View

GND

Vcc

RESET

SCK

8-pad UDFN

Top View

(through package)

GND

Vcc

RESET

SCK

Note:

The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.

This pad can be a “no connect” or connected to GND.

AT25PE16

DS-25PE16-143C–8/2018

Table 1-1.

Pin Configurations

Asserted

State

Symbol

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in the standby mode (not Deep Power-Down

mode) and the output pin (SO) will be in a high-impedance state. When the device is

deselected, data will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device will not enter the standby mode until the completion of

the operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is

always latched on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

Serial Input:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS

is deasserted).

Serial Output:

The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state

whenever the device is deselected (CS is deasserted).

Write Protect:

When the WP pin is asserted, all sectors specified for protection by the Sector

Protection Register will be protected against program and erase operations regardless of

whether the Enable Sector Protection command has been issued or not. The WP pin functions

independently of the software controlled protection method. After the WP pin goes low, the

contents of the Sector Protection Register cannot be modified.

Type

Low

Input

SCK

—

Input

—

Input

—

Output

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle

state once the CS pin has been deasserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected to

whenever possible.

Reset:

A low state on the reset pin (RESET) will terminate the operation in progress and reset

the internal state machine to an idle state. The device will remain in the reset condition as long

as a low level is present on the RESET pin. Normal operation can resume once the RESET pin

is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not utilized, then it is

recommended that the RESET pin be driven high externally.

Low

Input

RESET

Low

Input

GND

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

—

Power

Ground

AT25PE16

DS-25PE16-143C–8/2018

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