S25FS064S
64 Mbit (8 Mbyte), 1.8 V FS-S Flash
Features
Serial Peripheral Interface (SPI) with Multi-I/O
❐
SPI Clock polarity and phase modes 0 and 3
❐
Double Data Rate (DDR) option
❐
Extended Addressing: 24- or 32-bit address options
❐
Serial Command subset and footprint compatible with S25-
FL1-K, S25FL-P and S25FL-S SPI families
❐
Multi I/O Command subset and footprint compatible with
S25FL1-K S25FL-P and S25FL-S SPI families
Read
❐
Commands: Normal, Fast, Dual Output, Dual I/O, Quad Out-
put, Quad I/O, DDR Quad I/O
❐
Modes: Burst Wrap, Continuous (XIP), QPI (QPI)
❐
Serial Flash Discoverable Parameters (SFDP) and Common
Flash Interface (CFI), for configuration information.
Program
❐
256 or 512 Bytes Page Programming buffer
❐
Program suspend and resume
❐
Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase
❐
Hybrid sector option
• Physical set of eight 4KB sectors and one 32KB sector at
the top or bottom of address space with all remaining sec-
tors of 64KB
❐
Uniform sector option
• Uniform 64KB or 256KB blocks for software compatibility
with higher density and future devices
❐
Erase suspend and resume
❐
Erase status evaluation
Cycling Endurance
❐
100,000 Program-Erase Cycles, minimum
Data Retention
20 Year Data Retention, minimum
Security Features
❐
One Time Program (OTP) array of 1024 bytes
❐
Block Protection:
• Status Register bits to control protection against program
or erase of a contiguous range of sectors.
• Hardware and software control options
❐
Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
• Option for password control of read access
Technology
®
™
❐
Cypress 65 nm MirrorBit Technology with Eclipse Archi-
tecture
Single Supply Voltage with CMOS I/O
❐
1.7 V to 2.0 V
Temperature Range
❐
Industrial (
40 °C to +85 °C)
❐
Industrial Plus (
40 °C to +105 °C)
❐
Extended (
40 °C to +125 °C)
❐
Automotive, AEC-Q100 Grade 3 (
40 °C to +85 °C)
❐
Automotive, AEC-Q100 Grade 2 (
40 °C to +105 °C)
❐
Automotive, AEC-Q100 Grade 1 (
40 °C to +125 °C)
Packages (all Pb-free)
❐
8-lead SOIC 208 mil (SOC008)
❐
LGA 5x6 mm (W9A008)
❐
BGA-24 6
8 mm
• 5
5 ball (FAB024) footprint
❐
Cypress Semiconductor Corporation
Document Number: 002-03631 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 06, 2018
S25FL512S
Contents
Features.................................................................................
1
Logic Block Diagram............................................................
2
Performance Summary
........................................................ 3
1.
1.1
1.2
1.3
2.
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
6.2
6.3
6.4
6.5
7.
8.
8.1
8.2
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Other Resources............................................................
5
5
5
7
Software Interface
9.
9.1
9.2
9.3
9.4
9.5
9.6
10.
10.1
10.2
10.3
10.4
10.5
Address Space Maps..................................................
44
Overview....................................................................... 44
Flash Memory Array...................................................... 44
ID-CFI Address Space .................................................. 46
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space............................................................... 46
OTP Address Space ..................................................... 47
Registers....................................................................... 48
Data Protection
........................................................... 64
Secure Silicon Region (OTP)........................................ 64
Write Enable Command................................................ 64
Block Protection ............................................................ 65
Advanced Sector Protection ......................................... 66
Recommended Protection Process ............................. 71
Hardware Interface
Serial Peripheral Interface with Multiple Input / Output
(SPI-MIO).......................................................................
8
Signal Descriptions
..................................................... 8
Input/Output Summary................................................... 8
Multiple Input / Output (MIO).......................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1................................................. 9
Write Protect (WP#) / IO2 .............................................. 9
IO3_RESET# ............................................................... 10
RESET# ....................................................................... 10
Voltage Supply (VCC).................................................. 10
Supply and Signal Ground (V
SS
) ................................. 10
Not Connected (NC) .................................................... 10
Reserved for Future Use (RFU)................................... 10
Do Not Use (DNU) ....................................................... 11
System Block Diagrams............................................... 11
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Latchup Characteristics ...............................................
Thermal Resistance .....................................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics. .............................................
13
13
14
18
22
22
23
23
23
23
23
24
26
30
30
30
31
34
37
11. Commands
.................................................................. 72
11.1 Command Set Summary............................................... 73
11.2 Identification Commands .............................................. 79
11.3 Register Access Commands......................................... 82
11.4 Read Memory Array Commands .................................. 93
11.5 Program Flash Array Commands ............................... 101
11.6 Erase Flash Array Commands.................................... 104
11.7 One Time Program Array Commands ........................ 111
11.8 Advanced Sector Protection Commands .................... 111
11.9 Reset Commands ....................................................... 118
11.10DPD Commands......................................................... 119
12. Data Integrity
............................................................. 121
12.1 Erase Endurance ........................................................ 121
12.2 Data Retention ............................................................ 121
13. Software Interface Reference
.................................. 122
13.1 OTP Memory Space Address Map ............................. 122
13.2 Device ID and Common Flash Interface (ID-CFI) Address
Map — Standard......................................................... 122
13.3 Serial Flash Discoverable Parameters (SFDP) Address
Map ............................................................................. 128
13.4 Initial Delivery State .................................................... 140
14.
15.
16.
Ordering Part Number
.............................................. 141
Contacting Cypress
.................................................. 142
Glossary
.................................................................... 143
Embedded Algorithm Performance Tables..............
39
Physical Interface
...................................................... 40
Connection Diagrams .................................................. 40
Physical Diagrams ....................................................... 41
16. Document History Page
........................................... 144
Sales, Solutions, and Legal Information .........................146
Worldwide Sales and Design Support ..........................146
Products .......................................................................146
PSoC
®
Solutions ..........................................................146
Cypress Developer Community ....................................146
Technical Support ........................................................146
Document Number: 002-03631 Rev. *F
Page 4 of 146
S25FS064S
1.
1.1
Overview
General Description
The Cypress FS-S Family of devices are Flash non-volatile memory products using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
The FS-S Family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from Flash memory is often called Execute-In-Place or XIP. By using FS-S Family devices at the higher
clock rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FS-S Family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
1.2
1.2.1
Migration Notes
Features Comparison
The FS-S Family is command subset and footprint compatible with prior generation FL-S, and FL-P families. However, the power
supply and interface voltages are nominal 1.8V.
Table 1. Cypress SPI Families Comparison
Parameter
FS-S
FS-S
FL-S
FL-P
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Rate (typ.)
Page Programming Rate
(typ.)
OTP
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
65nm
MirrorBit
®
Eclipse™
In Production
128Mb, 256Mb 512MB
x1, x2, x4
1.7V - 2.0V
6MB/s (50MHz)
16.5MB/s (133MHz)
33MB/s (133MHz)
66MB/s (133MHz)
80MB/s (80 MHz)
256B / 512B
64KB / 256KB
4KB (option)
500 KB/s
1.0 MB/s (256B)
1.2 MB/s (512B)
1024B
Yes
No
Yes
65nm
MirrorBit
®
Eclipse™
2H2015
64Mb
x1, x2, x4
1.7V - 2.0V
6MB/s (50MHz)
16.5MB/s (133MHz)
33MB/s (133MHz)
66MB/s (133MHz)
80Mb/s(80Mhz )
256B / 512B
64KB / 256KB
4KB (option)
500 KB/s
1.0 MB/s (256B)
1.2 MB/s (512B)
1024B
Yes
No
Yes
65nm
MirrorBit
®
Eclipse™
In Production
128Mb 256Mb 512Mb
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V
V
IO
6MB/s (50MHz)
16.5MB/s (133MHz)
26MB/s (104MHz)
52MB/s (104MHz)
66MB/s (66MHz)
256B / 512B
64KB / 256KB
4KB (option)
500 KB/s
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
Yes
Yes
Yes
90nm
MirrorBit
®
In Production
32Mb - 256Mb
x1, x2, x4
2.7V - 3.6V
5MB/s (40MHz)
13MB/s (104MHz)
20MB/s (80MHz)
40MB/s (80MHz)
-
256B
64KB / 256KB
4KB
130 KB/s
170 KB/s
506B
No
No
No
Document Number: 002-03631 Rev. *F
Page 5 of 146
Embedded System
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