IS29GL256S-10DHB02-TR datasheet, PDF

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IS29GL256S-10DHB02-TR: DescriptionNOR flash memory; Categorysemiconductor Memory IC NOR flash memory; File Size2MB，109 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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IS29GL256S-10DHB02-TR Overview

NOR flash memory

IS29GL256S-10DHB02-TR Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	FBGA-64
series	S29GL01G/512/256/128S
storage	256 Mbit
Interface Type	Parallel
Timing type	Asynchronous
Data bus width	16 bit
Supply voltage - min.	2.7 V
Supply voltage - max.	3.6 V
Supply current—max.	100 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 105 C
Encapsulation	Reel
storage type	NOR
speed	100 ns
structure	MirrorBit Eclipse
standard	Common Flash Interface (CFI)
Factory packaging quantity	2200

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S29GL01GS/S29GL512S

S29GL256S/S29GL128S

1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/

256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte),

3.0 V, GL-S Flash Memory

General Description

The Cypress

S29GL01G/512/256/128S are MirrorBit

Eclipse flash products fabricated on 65 nm process technology. These

devices offer a fast page access time as fast as 15 ns with a corresponding random access time as fast as 90 ns. They feature a

Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective

programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that

require higher density, better performance and lower power consumption.

Distinctive Characteristics



CMOS 3.0 Volt Core with Versatile I/O



65 nm MirrorBit Eclipse Technology



Single supply (V

) for read / program / erase (2.7 V to

3.6 V)



Versatile I/O Feature

– Wide I/O voltage range (V

): 1.65 V to V



×16 data bus



Asynchronous 32-byte Page read



512-byte Programming Buffer

– Programming in Page multiples, up to a maximum of

512 bytes



Single word and multiple program on same word options



Automatic Error Checking and Correction (ECC) – internal

hardware ECC with single bit error correction



Sector Erase

– Uniform 128-kbyte sectors



Suspend and Resume commands for Program and Erase

operations



Status Register, Data Polling, and Ready/Busy pin methods

to determine device status



Advanced Sector Protection (ASP)

– Volatile and non-volatile protection methods for each

sector



Separate 1024-byte One Time Program (OTP) array with two

lockable regions



Common Flash Interface (CFI) parameter table



Temperature Range / Grade

– Industrial (-40 °C to +85 °C)

– Industrial Plus(-40 °C to +105 °C)

– Automotive, AEC-Q100 Grade 3 (-40 °C to +85 °C)

– Automotive, AEC-Q100 Grade 2 (-40 °C to +105 °C)



100,000 Program / Erase Cycles



20 Years Data Retention



Packaging Options

– 56-pin TSOP

– 64-ball LAA Fortified BGA, 13 mm × 11 mm

– 64-ball LAE Fortified BGA, 9 mm × 9 mm

– 56-ball VBU Fortified BGA, 9 mm × 7 mm

Cypress Semiconductor Corporation

Document Number: 001-98285 Rev. *R

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 21, 2018

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

Table 1.1

S29GL-S Address Map

Type

Address within Page

Address within Write Buffer

Page

Write-Buffer-Line

Count

256

4096

256

1024 (1 Gb)

512 (512 Mb)

256 (256 Mb)

128 (128 Mb)

Addresses

A3–A0

A7–A0

A15–A4

A15–A8

Sector

MAX

–A16

The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded

Algorithm Controller (EAC). HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and write

data transfers with the host system. HIC delivers data from the currently entered address map on read transfers; places write

transfer address and data information into the EAC command memory; notifies the EAC of power transition, hardware reset, and

write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and performs the

related Embedded Algorithms.

Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded

Algorithms (EA). The algorithms are managed entirely by the device internal EAC. The main algorithms perform programming and

erase of the main array data. The host system writes command codes to the flash device address space. The EAC receives the

commands, performs all the necessary steps to complete the command, and provides status information during the progress of an

EA.

The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an Erase operation

is able to change a 0 to a 1. An erase operation must be performed on an entire 128-kbyte aligned and length group of data call a

Sector. When shipped from Cypress all Sectors are erased.

Programming is done via a 512-byte Write Buffer. It is possible to write from 1 to 256 words, anywhere within the Write Buffer before

starting a programming operation. Within the flash memory array, each 512-byte aligned group of 512 bytes is called a Line. A

programming operation transfers volatile data from the Write Buffer to a non-volatile memory array Line. The operation is called

Write Buffer Programming.

As the device transfers each 32-byte aligned page of data that was loaded into the Write buffer to the 512-byte Flash array line,

internal logic programs an ECC Code for the Page into a portion of the memory array not visible to the host system software. The

internal logic checks the ECC information during the initial access of every array read operation. If needed, the ECC information

corrects a one bit error during the initial access time.

The Write Buffer is filled with 1’s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0

by a Write to Buffer command are by default still filled with 1’s. Any 1’s in the Write Buffer do not affect data in the memory array

during a programming operation.

As each Page of data that was loaded into the Write Buffer is transferred to a memory array Line.

Sectors may be individually protected from program and erase operations by the Advanced Sector Protection (ASP) feature set.

ASP provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected

from program and erase operations.

Document Number: 001-98285 Rev. *R

Page 5 of 108

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