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ispLSI 2096A-80LQN128I

Description
CPLD - Complex Programmable Logic Device USE ispMACH 4000V
Categorysemiconductor    Programmable logic IC    CPLD - complex programmable logic devices   
File Size400KB,13 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Environmental Compliance
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ispLSI 2096A-80LQN128I Overview

CPLD - Complex Programmable Logic Device USE ispMACH 4000V

ispLSI 2096A-80LQN128I Parametric

Parameter NameAttribute value
MakerLattice
Product CategoryCPLD - Complex Programmable Logic Device
productispLSI 2096A
Large battery quantity96
Number of logical array blocks - LAB24
Maximum operating frequency83 MHz
Propagation Delay—Max.15 ns
Number of input/output terminals96 I/O
Working power voltage5 V
Minimum operating temperature- 40 C
Maximum operating temperature+ 85 C
Installation styleSMD/SMT
Package/boxPQFP-128
EncapsulationTray
high3.4 mm
length28 mm
seriesispLSI 2096/A
width28 mm
Number of gates4000
Working power current295 mA
Factory packaging quantity24
Supply voltage - max.5.5 V
Supply voltage - min.4.5 V
Lead-
Free
Package
Options
Available!
ispLSI 2096/A
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
®
Features
• ENHANCEMENTS
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
— ispLSI 2096A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
4000 PLD Gates
96 I/O Pins, Six Dedicated Inputs
96 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E CMOS TECHNOLOGY
2
®
C7
A0
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
S
N
B2
B3
B6
Output Routing Pool (ORP)
B7
Select devices have been discontinued.
See Ordering Information section for product status.
D Q
A1
A2
ES
IG
B0
B1
GLB
Logic
Array
D Q
D Q
Global Routing Pool
(GRP)
B5
D Q
A3
A4
A5
A6
A7
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
D
0919/2096
f
max
= 125 MHz Maximum Operating Frequency
t
pd
= 7.5 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
09
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
6E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
The ispLSI 2096 and 2096A are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
U
SE
is
p
LS
I2
FO
R
N
EW
Description
August 2006
2096_09
1

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Description CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V CPLD - Complex Programmable Logic Device USE ispMACH 4000V
Maker Lattice Lattice Lattice Lattice Lattice Lattice Lattice Lattice Lattice
Product Category CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device
product ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A ispLSI 2096A
Large battery quantity 96 96 96 96 96 96 96 96 96
Number of logical array blocks - LAB 24 24 24 24 24 24 24 24 24
Maximum operating frequency 83 MHz 100 MHz 83 MHz 83 MHz 100 MHz 125 MHz 83 MHz 100 MHz 83 MHz
Propagation Delay—Max. 15 ns 13 ns 18.5 ns 15 ns 13 ns 10 ns 18.5 ns 13 ns 18.5 ns
Number of input/output terminals 96 I/O 96 I/O 96 I/O 96 I/O 96 I/O 96 I/O 96 I/O 96 I/O 96 I/O
Working power voltage 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Minimum operating temperature - 40 C 0 C 0 C 0 C 0 C 0 C - 40 C 0 C 0 C
Maximum operating temperature + 85 C + 70 C + 70 C + 70 C + 70 C + 70 C + 85 C + 70 C + 70 C
Installation style SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package/box PQFP-128 PQFP-128 TQFP-128 TQFP-128 TQFP-128 TQFP-128 TQFP-128 PQFP-128 PQFP-128
Encapsulation Tray Tray Tray Tray Tray Tray Tray Tray Tray
high 3.4 mm 3.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 1.4 mm 3.4 mm 3.4 mm
length 28 mm 28 mm 14 mm 14 mm 14 mm 14 mm 14 mm 28 mm 28 mm
series ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A ispLSI 2096/A
width 28 mm 28 mm 14 mm 14 mm 14 mm 14 mm 14 mm 28 mm 28 mm
Number of gates 4000 4000 4000 4000 4000 4000 4000 4000 4000
Working power current 295 mA 295 mA 295 mA 295 mA 295 mA 295 mA 150 mA 295 mA 295 mA
Factory packaging quantity 24 24 90 90 90 90 90 24 24
Supply voltage - max. 5.5 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.5 V 5.25 V 5.25 V
Supply voltage - min. 4.5 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.5 V 4.75 V 4.75 V
storage type - EEPROM EEPROM - - - EEPROM EEPROM EEPROM
unit weight - - 503.500 mg 503.500 mg 503.500 mg 503.500 mg 503.500 mg - -
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