NCP81239, NCP81239A
USB Power Delivery
4-Switch Buck Boost
Controller
The NCP81239 USB Power Delivery (PD) Controller is a
synchronous buck boost that is optimized for converting battery
voltage or adaptor voltage into power supply rails required in
notebook, tablet, and desktop systems, as well as many other
consumer devices using USB PD standard and C−Type cables. The
NCP81239 is fully compliant to the USB Power Delivery
Specification when used in conjunction with a USB PD or C−Type
Interface Controller. NCP81239 is designed for applications requiring
dynamically controlled slew rate limited output voltage that require
either voltage higher or lower than the input voltage. The NCP81239
drives 4 NMOSFET switches, allowing it to buck or boost and support
the functions specified in the USB Power Delivery Specification
which is suitable for all USB PD applications. The USB PD Buck
Boost Controller operates with a supply and load range of 4.5 V to 32
V. NCP81239A is functionally same as NCP81239 except with
different I
2
C address.
Features
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1
32
QFN32 5x5, 0.5P
CASE 485CE
MARKING DIAGRAM
1
1
NCP81239
AWLYYWWG
G
81239A
AWLYYWWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input Voltage Range: from 4.5 V to 32 V
Dynamically Programmed Frequency from 150 kHz to 1.2 MHz
I
2
C Interface
Real Time Power Good Indication
Controlled Slew Rate Voltage Transitioning
Feedback Pin with Internally Programmed Reference
Support USBPD/QC2.0/QC3.0 Profile
2 Independent Current Sensing Inputs
Over Temperature Protection
Adaptive Non−Overlap Gate Drivers
Filter Capacitor Switch Control
Over−Voltage and Over−Current Protection
Dead Battery Power Support
5 x 5 mm QFN32 Package
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Typical Application
•
•
•
•
•
•
•
Notebooks, Tablets, Desktops
All in Ones
Monitors, TVs, and Set Top Boxes
Consumer Electronics
Car Chargers
Docking Stations
Power Banks
ORDERING INFORMATION
Device
NCP81239MNTXG
NCP81239AMNTXG
Package
QFN32
(Pb−Free)
QFN32
(Pb−Free)
Shipping
†
2500 / Tape
& Reel
2500 / Tape
& Reel
I
2
C Address
74H
75H
†For information on tape and reel specifications, including part orientation
and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
May, 2018
−
Rev. 6
1
Publication Order Number:
NCP81239/D
NCP81239, NCP81239A
V1
V1
CSP1
RS1
Q6
V2
5V Rail
Dead Battery /
VCONN
C
VDRV
R
DRV
DBIN
DBOUT
VDRV
CSN1
FB
VCC
RPU
CO1
RS2
Q5
RPD
CO2
VBUS
C
VCC
CSN2
CSP2
Current Sense 1
R
CS1
CS1
CFET1
BST2
Current Sense 2
R
CS2
CS2
BST1
S1
CB1
CB2
S4
Curret Limit Indicator
Interrupt
Enable
I2C
CLIND
INT
EN
SDA
SCL
HSG1
VSW1
HSG2
VSW2
L1
S2
LSG1
COMP
CP
RC
PGND1
LSG2
PGND2
S3
CC
AGND
FLAG
PDRV
Figure 1. Typical Application Circuit
DBOUT
VSW1
VSW2
26
VDRV
BST1
32
HSG1
LSG1
PGND1
CSN1
CSP1
V1
CS1
CLIND
1
2
3
4
5
6
7
8
9
SDA
31
30
29
28
27
25
24
23
22
21
HSG2
LSG2
PGND2
CSP2
CSN2
FB
CS2
PDRV
Exposed Thermal Pad
BST2
20
19
18
17
16
EN
10
SCL
11
INT
12
CFET
13
AGND
DBIN
VCC
14
AGND
15
COMP
Figure 2. Pinout
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2
NCP81239, NCP81239A
DBOUT
DBIN
Current Limiting
Circuit
For Dead Battery
CONFIG
+
CONFIG
CL2N
CL2P
+
−
−
CL2N REF
V1
BG
V1
CSP1
CSP1
+
Boot1V
CS2_INT
CL2P REF
Thermal
Shutdown
TS
CS1
CS1_INT
+
CSN1
BST1
HSG1
VSW1
Q1
+
VCC
4.0V
−
CONFIG
CL1N
CL1P
+
−
−
CL1N REF
VCC
VDRV
VDRV
Startup
INPUT
UVLO
+
BG
IUVLOB
Boot1 _UVLO
CS1_INT
CL1P REF
+
VDRV_rdy
CONFIG
CL2
CL1
SW1
SW2
SW3
SW4
IUVLOB
PG
TS
EN
CS1
4.0V
NOL
Drive
Logic_1
−
VDRV
CS1
+
CLINDP1
CLIND
CLINDP2
NC
CS2
CLIND
CLIMP1
CLIMP2
−
−
+
Control
Logic
CS2
CLIND
EN
−
EN
LOGIC
0.8V
+
EN_MASK
ENPOL
EN
ADC
Value
Register
Analog
Mux
CSP1
VFB
CS1_INT
CS2_INT
PG_Low
−
+
OV_MSK
NOL
Drive
Logic_2
VDRV
VFB
−
+
PG/
OV/
LOGIC
PG_MSK
OV
PG
+
PG_High
+
OV_REF
−
Ramp_0
∑
CS1_INT
CS2_INT
SCL
INT
I2C
Interface
Digital
Configuration
Oscillator
VDRV
CFET
PDRV
Ramp_180
∑
CS1_INT
CONFIG
Reference
INT
Interface
Status
Registers
PG
TS
VFB
BG
180_Ramp
−
VDRV
COMP
CC
CP
RC
Error OTA
500μS/100μS
+
_
Buck Logic
+
−
Boost Logic
Buck Boost
Logic
+
0_Ramp
VFB
AGND
FLAG
Figure 3. Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
2
3, 22
4
5
6
7
8
9
10
11
12
Pin Name
HSG1
LSG1
PGND
CSN1
CSP1
V1
CS1
CLIND
SDA
SCL
INT
CFET
Description
S1 gate drive. Drives the S1 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch
node voltage VSW1.
Drives the gate of the S2 N−channel MOSFET between ground and VDRV.
Power ground for the low side MOSFET drivers. Connect these pins closely to the source of the bottom
N−channel MOSFETs.
Negative terminal of the current sense amplifier.
Positive terminal of the current sense amplifier.
Input voltage of the converter
Current sense amplifier output. CS1 will source a current that is proportional to the voltage across RS1 to an
external resistor. CS1 voltage can be monitored with a high impedance input. Ground this pin if not used.
Open drain output to indicate that the CS1 or CS2 voltage has exceeded the I
2
C programmed limit.
I
2
C interface data line.
I
2
C interface clock line.
Interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and oth-
er I
2
C programmable functions.
Controlled drive of an external MOSFET that connects a bulk output capacitor to the output of the power
converter. Necessary to adhere to low capacitance limits of the standard USB Specifications for power prior to
USB PD negotiation.
The ground pin for the analog circuitry.
Output of the transconductance amplifier used for stability in closed loop operation.
13−14
15
AGND
COMP
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3
_
SDA
CONFIG
0_Ramp
CS2_INT
CSN2
+
CFET
PDRV
Boot2 _UVLO
Boot1V
Limit
Registers
VFB
CS2
_
Vcc_rdy
V1
V2
LSG1
PGND1
PGND2
LSG2
VSW2
HSG2
BST2
CSP2
CSN2
CFET
CO
CO2
Q2
PDRV
SW1
SW2
SW3
SW4
FB
NCP81239, NCP81239A
Table 1. PIN FUNCTION DESCRIPTION
Pin
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
33
Pin Name
EN
PDRV
CS2
FB
CSN2
CSP2
LSG2
HSG2
BST2
VSW2
DBOUT
DBIN
VDRV
VCC
VSW1
BST1
THPAD
Description
Precision enable starts the part and places it into default configuration when toggled.
The open drain output used to control a PMOSFET.
Current sense amplifier output. CS2 will source a current that is proportional to the voltage across RS2 to an
external resistor. CS2 voltage can be monitored with a high impedance input. Ground this pin if not used.
Feedback voltage of the output, negative terminal of the gm amplifier.
Negative terminal of the current sense amplifier.
Positive terminal of the current sense amplifier.
Drives the gate of the S3 N−channel MOSFET between ground and VDRV.
S4 gate drive. Drives the S4 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch
node voltage VSW2.
Bootstrapped Driver Supply. The BST2 pin swings from a diode voltage below VDRV up to a diode voltage
below VOUT + VDRV. Place a 0.1
mF
capacitor from this pin to VSW2.
Switch Node. VSW2 pin swings from a diode voltage drop below ground up to output voltage.
The output of the dead battery circuit which can also be used for the VCONN voltage supply.
The dead battery input to the converter where 5 V is applied. A 1
mF
capacitor should be placed close to the
part to decouple this line.
Internal voltage supply to the driver circuits. A 1
mF
capacitor should be placed close to the part to decouple
this line.
The VCC pin supplies power to the internal circuitry. The VCC is the output of a linear regulator which is pow-
ered from V1. Pin should be decoupled with a 1
mF
capacitor for stable operation.
Switch Node. VSW1 pin swings from a diode voltage drop below ground up to V1.
Driver Supply. The BST1 pin swings from a diode voltage below VDRV up to a diode voltage below V1 +
VDRV. Place a 0.1
mF
capacitor from this pin to VSW1.
Center Thermal Pad. Connect to AGND externally.
Table 2. MAXIMUM RATINGS
Over operating free−air temperature range unless otherwise noted
Rating
Input of the Dead Battery Circuit
Output of the Dead Battery Circuit
Driver Input Voltage
Internal Regulator Output
Output of Current Sense Amplifiers
Current Limit Indicator
Interrupt Indicator
Enable Input
I
2
C Communication Lines
Compensation Output
V1 Power Stage Input Voltage
Positive Current Sense
Negative Current Sense
Positive Current Sense
Negative Current Sense
Feedback Voltage
Symbol
DBIN
DBOUT
VDRV
VCC
CS1, CS2
CLIND
INT
EN
SDA, SCL
COMP
V1
CSP1
CSN1
CSP2
CSN2
FB
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
Max
5.5
5.5
5.5
5.5
3.0
VCC + 0.3
VCC + 0.3
5.5
VCC + 0.3
VCC + 0.3
32 V, 40 V (20 ns)
32 V, 40 V (20 ns)
32 V, 40 V (20 ns)
32 V, 40 V (20 ns)
32 V, 40 V (20 ns)
5.5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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NCP81239, NCP81239A
Table 2. MAXIMUM RATINGS
Over operating free−air temperature range unless otherwise noted
Rating
CFET Driver
Driver 1 and Driver 2 Positive Rails
High Side Driver 1 and Driver 2
Switching Nodes and Return Path of Driver 1 and
Driver 2
Low Side Driver 1 and Driver 2
PMOSFET Driver
Voltage Differential
CSP1−CSN1, CSP2−CSN2 Differential Voltage
PDRV Maximum Current
PDRV Maximum Pulse Current
(100 ms on time, with > 1 s interval)
Maximum VCC Current
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
Thermal Characteristics (Note 2)
QFN 32 5mm x 5mm
Maximum Power Dissipation @ TA = 25°C
Maximum Power Dissipation @ TA = 85°C
Thermal Resistance Junction−to−Air with Solder
Thermal Resistance Junction−to−Case Top with Solder
Thermal Resistance Junction−to−Case Bottom with Sol-
der
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free (Note 3)
Symbol
CFET
BST1,
BST2
HSG1,
HSG2
VSW1,
VSW2
LSG1,
LSG2
PDRV
AGND to
PGND
CS1DIF,
CS2DIF
PDRVI
PDRVIPUL
VCCI
TJ
TA
TSTG
Min
−0.3
−0.3
V wrt/PGND
−0.3
V wrt/VSW
−0.3
V wrt/PGND
−0.3
V wrt/VSW
−5.0
V
−0.3
V
−0.3
−0.3
−0.5
0
0
0
−40
−40
−55
Max
VCC + 0.3
37 V, 40 V (20 ns) wrt/PGND
5.5 V wrt/VSW
37 V, 40 V (20 ns) wrt/GND
5.5 V wrt/VSW
32 V, 40 V (20 ns)
5.5
32 V, 40 V (20 ns)
0.3
0.5
10
200
80
150
100
150
Unit
V
V
V
V
V
V
V
V
mA
mA
mA
°C
°C
°C
PD
PD
RQJA
RQJCT
RQJCB
RF
4.1
2.1
30
1.7
2.0
260 Peak
W
W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum package power dissipation limit must not be exceeded.
2. The value of
QJA
is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch FR−4 board with 1.5 oz. copper on the top and
bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with T
A
= 25°C.
3. 60−180 seconds minimum above 237°C.
Table 3. ELECTRICAL CHARACTERISTICS
(V1 = 12 V, V
out
= 1.0 V , T
A
= +25°C for typical value;
−40°C
< T
A
< 100°C for min/max values unless noted otherwise)
Parameter
Power Supply
V1 Operating Input Voltage
VDRV Operating Input Voltage
VCC UVLO Rising Threshold
UVLO Hysteresis for VCC
VDRV UVLO Rising Threshold
UVLO Hysteresis for VDRV
V1
VDRV
VCC
START
VCCV
HYS
VDRV
START
VDRV
HYS
Falling Hysteresis
Falling Hysteresis
4.5
4.5
5
4.3
300
4.3
300
32
5.5
V
V
V
mV
V
mV
Symbol
Test Conditions
Min
Typ
Max
Units
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