NXP Semiconductors
Data Sheet: Technical Data
Document Number S32V234
Rev. 8, 01/2019
S32V234 Data Sheet
Features
• ARM® Cortex®-A53, 64-bit CPU
– Up to 1000 MHz Quad ARM Cortex-A53
– 32 KB/32 KB I-/D- L1 Cache
– NEON MPE co-processor
– Dual precision FPU
– 2 clusters with 2 CPUs and 256 KB L2 cache each
– Memory Management Unit
– GIC Interrupt Controller
– ECC/parity error support for its memories
– Generic timers
– Fault encapsulation by hardware for redundant
executed application software on multiple core
cluster
• ARM Cortex-M4, 32-bit CPU
– Up to 133 MHz
– 16 KB/16 KB I-/D- L1 Cache
– 32+32 KB tightly coupled memory (TCM)
– ECC/parity support for its memories
• Clocks
– Phase Locked Loops (PLLs)
– 1 external crystal oscillator (FXOSC)
– 1 FIRC oscillator
• System protection and power management features
– Flexible run modes to consume low power based on
application needs
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Power gating of unused A53 cores and GPU
– Low and high voltage warning and detect
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 120-bit unique chip identifier
– Hardware watchdog
– eDMA controller with 32 channels (with
DMAMUX)
– Extended Resource Domain Controller
S32V234
• Safety concept
– ISO 26262, ASIL level target
– Measures to detect faults in memory and logic
– Measures to detect single point and latent faults
– Quantitative out of context analysis of functional
safety (FMEDA) tailored to application specifics
– Safety manual and FMEDA report available
• Security
– CSE with 16 KB of on-chip Secure RAM and ROM.
– Secure vs non-secure applications separation
supported via ARM v8 exception level support in
the ARM Cortex A53 clusters and its extension via
XRDC on chip level.
– Boot from NOR flash with AES-128 (CTR)
– On-Chip One-Time Programmable element
Controller (OCOTP_CTRL) with on chip electrical
fuse array.
– System JTAG Controller (SJC)
• Debug functionality
– Standard JTAG and Compact JTAG
– 16-bit Trace port, Serial Wire Output port
• Timers
– General purpose timers (FTM)
– Two Periodic Interrupt Timer (PIT)
– IEEE 1588 Timers (part of Ethernet Subsystem)
• Analog
– 1x 12-bit 1.8 V SAR ADC with self-test
• Communications
– UART(w/ LIN2.1l)
– Serial peripheral interface (SPI)
– I2C blocks
– PCI express 2.0 with endpoint and root complex
support
– LFAST serial link
– 1 GBit Ethernet with PTP IEEE 1588
– FD-CAN
– FlexRay Dual Channel, Version 2.1 RevA
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Memory interfaces
– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock
frequency with ECC (SEC-DED-TED) triple error detection support for subregion
– QuadSPI supporting Execute-In-Place (XIP)
– Boot flash fault detection and correction using two-dimensional parity.
– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display
– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding
– GPU GC3000 with frame buffer compression
– 2x VIU (Video interface unit) for camera input
– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions
(exposure control, gamma correction)
– 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) cores
configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMD
engines with 32 16-bit CUs each.
– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter
– JPEG video decoder (8/12-bit)
– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats
– H.264 video encode (8/10/12-bit), High-intra only
– Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter
– Configurable slew rate and drive strength on all output pins
• System RAM
– 4 MB On-Chip System RAM with ECC
S32V234 Data Sheet, Rev. 8, 01/2019
2
NXP Semiconductors
Table of Contents
1
2
Block diagram.................................................................................... 5
Family comparison.............................................................................5
2.1
3
Feature Set...............................................................................5
6.4
6.3
Memory interfaces...................................................................26
6.3.1
QuadSPI AC specifications....................................... 26
DDR SDRAM Specific Parameters (DDR3, DDR3L, and
LPDDR2)................................................................................ 31
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
DDR3 and DDR3L timing parameters ..................... 31
DDR3 and DDR3L read cycle...................................33
DDR3 and DDR3L write cycle................................. 34
LPDDR2 timing parameter........................................35
LPDDR2 read cycle...................................................37
LPDDR2 write cycle................................................. 38
Ordering parts.....................................................................................8
3.1
4
Ordering information...............................................................8
General............................................................................................... 8
4.1
4.2
4.3
Operation above maximum operating conditions................... 8
Recommended operating conditions....................................... 9
Power Management Controller (PMC) electrical
specifications...........................................................................10
4.4
4.5
4.6
4.7
Power consumption................................................................. 11
Electrostatic discharge (ESD) specifications.......................... 13
Electromagnetic Compatibility (EMC) specifications............ 13
PCB routing guidelines........................................................... 13
Communication modules.........................................................39
6.5.1
6.5.2
DSPI timing............................................................... 39
Ultra High Speed SD/SDIO/MMC Host Interface
(uSDHC)....................................................................43
6.5.2.1
6.5.2.2
6.5.3
SDR mode timing specifications........... 43
DDR mode timing specifications...........45
5
I/O parameters....................................................................................15
5.1
General purpose I/O parameters..............................................15
5.1.1
5.1.2
5.2
GPIO speed at various voltage levels........................ 15
DC electrical specifications....................................... 17
LFAST electrical characteristics............................... 48
6.5.3.1
6.5.3.2
LFAST interface timing diagrams......... 48
LFAST Interface electrical
characteristics........................................ 49
DDR pads................................................................................ 18
5.2.1
DDR3 mode...............................................................18
5.2.1.1
DDR3 mode DC electrical
specifications......................................... 18
5.2.2
DDR3L mode............................................................ 18
5.2.2.1
DDR3L mode DC electrical
specifications......................................... 18
5.2.3
LPDDR2 mode.......................................................... 19
5.2.3.1
LPDDR2 mode DC electrical
specifications......................................... 19
6.5.5
6.5.4
FlexRay......................................................................50
6.5.4.1
6.5.4.2
6.5.4.3
6.5.4.4
FlexRay timing parameters....................50
TxEN......................................................50
TxD........................................................ 51
RxD........................................................52
Ethernet Controller (ENET) Parameters................... 53
6.5.5.1
6.5.5.2
Ethernet Switching Specifications......... 53
Receive and Transmit signal timing
specifications for RMII interfaces......... 53
6.5.5.3
Receive and Transmit signal timing
specifications for MII interfaces............ 54
6.5.5.4
Receive and Transmit signal timing
specifications for RGMII interfaces...... 56
6.5.5.5
MII/RMII Serial Management channel
timing (MDC/MDIO)............................ 57
5.3
6
Boot Configuration Pins Specification....................................19
Peripheral operating requirements and behaviors.............................. 20
6.1
Analog modules.......................................................................20
6.1.1
ADC electrical specifications.................................... 20
6.1.1.1
6.1.2
6.2
Input equivalent circuit.......................... 21
Thermal Monitoring Unit (TMU)..............................23
Clocks and PLL interfaces modules........................................23
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Main oscillator electrical characteristics................... 23
48 MHz FIRC electrical characteristics.................... 24
PLL electrical specifications..................................... 24
DFS electrical specifications..................................... 25
LFAST PLL Electrical Specifications.......................25
6.6
6.5.6
6.5.7
6.5.8
PCI Express specifications........................................ 58
IIC timing.................................................................. 59
LINFlex timing.......................................................... 60
Display modules......................................................................61
6.6.1
Display Control Unit (2D-ACE) Parameters.............61
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors
3
6.6.1.1
6.6.1.2
Interface to TFT panels..........................61
Interface to TFT LCD Panels—Pixel
Level Timings........................................ 62
7
6.10 External interrupt timing (IRQ pin)........................................ 74
Thermal attributes.............................................................................. 75
7.1
8
Thermal attributes................................................................... 75
6.6.1.3
Interface to TFT LCD panels—access
level........................................................63
Dimensions.........................................................................................76
8.1
Obtaining package dimensions ...............................................76
6.6.2
6.6.3
Video input unit (VIU) timing specifications............64
MIPICSI2 D-PHY electrical and timing parameters.65
6.6.3.6
NOTICE OF DISCLAIMER................. 68
9
Pinouts................................................................................................76
9.1
Package pinouts and signal descriptions................................. 76
10 Reset sequence................................................................................... 76
10.1 Reset sequence duration.......................................................... 76
10.2 Boot performance matrix........................................................ 77
10.3 Reset sequence description......................................................78
11 Power sequencing requirements.........................................................80
12 Revision history................................................................................. 81
6.7
Debug specifications............................................................... 69
6.7.1
6.7.2
JTAG interface timing............................................... 69
Debug trace timing specifications............................. 73
6.8
6.9
Wakeup Unit (WKPU) AC specifications.............................. 74
RESET pin glitch filter specifications.....................................74
S32V234 Data Sheet, Rev. 8, 01/2019
4
NXP Semiconductors
Block diagram
1 Block diagram
GIC-400
Core0 Debug
1000MHz
Cortex-A53
NEON/FPU
32KB 32KB
I-Cache D-Cache
Core1 Debug
Core2 Debug
1000MHz
1000MHz
Cortex-A53
Cortex-A53
NEON/FPU
NEON/FPU
32KB 32KB 256KB 32KB 32KB
I-Cache D-Cache L2- I-Cache D-Cache
Cache
Core3 Debug
1000MHz
Cortex-A53
NEON/FPU
32KB 32KB 256KB
I-Cache D-Cache L2-
Cache
24-bit
RGB
Display IF
Debug
APEX-2_0
(2xAPU)
CMEM
16x 2Kx64
32KB 32KB
IMEM DMEM
MEMIF Seq
BlkDMA DMA
MC
128-
bits
Debug
APEX-2_1
(2xAPU)
CMEM
16x 2Kx64
32KB 32KB
IMEM DMEM
Seq MEMIF
BlkDMA DMA
MC
128-
bits
CRC
Display
Control
Unit
GPU
(2D-ACE)
GC3000
Fast
DMA
320 Mbps
10 Mbps
4 Lanes
4 Lanes
100MHz
100MHz
5 Gbps
1 Gbps
PCIe
Ethernet AVB
16-bit VIU
16-bit VIU
128-bits
CCI-400 incl. EDC
128-bits
128-bits
SRAM - all others
64-bits AHB
128-bits
SIPI+LFAST
FlexRay
SDHC
SCU
SCU
NVIC
64KB
CoreP
133MHz TCM
Cortex-
M4
Debug
16KB 16KB
I-Cache D-Cache
64-bits
AHB
64-bits
AHB
MC
64-
bits
CDC420
Encoder
64-
bits
DEC200 DEC200
Decoder Encoder
64-
bits
128-
bits
Cortex-A53
Debug
Concentrator
64-bits
AHB
64-bits
AHB
DMA
MEM
eDMA
CSE-FL Security
Engine
16KB
DRAM
1KB
ROM FUSE IF
Sideband
BIU Outputs
64-bits
ChanMux
64-bits
AHB
32-bits 64-bits
AHB
AHB
H.264 Dec
GPU
DCU
APEX-2_0
APEX-2_1
FastDMA
all others
PCIe/ENET
Cores
VIU_H264
APEX-2_0
APEX-2_1
FastDMA
all others
PCIe/ENET
Cores
XRDC
SEQ
XRDC
128-
bits
Hierarchical NIC 301 AXI Bus System incl. EDC
XRDC
XRDC
128-bits
128-
bits
AXBS Bus System incl. EDC
32-bits
64-bits
DRAM - SRAM -
all others all others
64-bits
64-bits
XRDC
64-bits
ChanMux
64-bits
AHB
ROM
Ctrl
32-bits
64-bits
64-bits
Debug
MIPI-CSI2
MIPI-CSI2
ISP0
ISP1
ISP2
•••
ISPN
H.264 Encoder
H.264 Decoder
JPEG Decoder
QoS 301 incl. EDC
XRDC
DRAM-ECC
DRAM-ECC
OTFAD
Peripheral
Bridge 1
32-bits
Debug
SRAM Controller
Multi Ported
Multi Banked
QuadSPI
NOR Flash Ctrl
2x4-bits
Peripheral
Bridge 0
32-bits
4KB
PRAM
64KB
CRAM
16KB
KRAM
MC
32-bit MMDC_0
LPDDR2
DDR3(L)
DDR-PHY
533 MHz
1066 MT/s
DDR
32-bit MMDC_1
LPDDR2
DDR3(L)
DDR-PHY
533 MHz
1066 MT/s
DDR
4/2x4/8-bits
QSPI Flash
External NOR Flash
Off-Chip
64 KB
ROM
(boot)
SWT_0
SWT_1
STM_0
PIT_0
STCU
MC
CGM, RGM,
PCU, ME
Sequencer
MPU
Figure 1. Block diagram
2 Family comparison
2.1 Feature Set
This family of devices supports the following features:
Table 1. Feature Set
Feature
ARM Cortex-A53 Core
•
•
•
•
•
•
•
S32V234
Up to 1000 MHz Quad ARM Cortex-A53
32 KB/32 KB I-/D- L1 Cache
NEON MPE co-processor
Dual precision FPU
256 KB L2 Cache per cluster
MMU
GIC interrupt controller
Table continues on the next page...
S32V232
• Up to 1000 MHz Dual ARM Cortex-A53
(single cluster)
• The remaining features are same as
S32V234
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors
5
SIUL
Wake Up
OCOTP_CTRL
SARADC_0
FlexTimer_0
IIC_0
Linflex_0
CAN_FD_0
DSPI_0
DSPI_2
CRC_0
4MB SRAM
24+Banks
ECC x64 Internal
MEMU
SEMA4
MSCM
ERM + EIM
PMC
TSENS
SSE
PIT_1
CGM-CMUs
INTC_MON
STM_1
SWT_2
SWT_3
SWT_4
FlexTimer_1
IIC_1
IIC_2
Linflex_1
CAN_FD_1
DSPI_1
DSPI_3
CRC_1
FCCU
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