Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 5
Release Information .............................................................................................................................................. 5
Device Support...................................................................................................................................................... 5
Chapter 2. Functional Description ........................................................................................................ 6
Functional overview .............................................................................................................................................. 6
Block Diagram....................................................................................................................................................... 8
Mathematical Model .............................................................................................................................................. 9
Filter Selection .................................................................................................................................................... 10
CFR Performance ............................................................................................................................................... 12
Primary I/O .......................................................................................................................................................... 14
Interface Descriptions ......................................................................................................................................... 18
Data Input/Output....................................................................................................................................... 18
Control Signals and Timing ........................................................................................................................ 18
Recommended CFR Coefficients Generation............................................................................................ 19
DSP Utilization Estimation ......................................................................................................................... 20
Chapter 3. Parameter Settings ............................................................................................................ 21
Architecture Tab.................................................................................................................................................. 23
Coefficients Tab .................................................................................................................................................. 24
Others Tab .......................................................................................................................................................... 25
Chapter 4. IP Core Generation............................................................................................................. 27
Licensing the IP Core.......................................................................................................................................... 27
IP Core Generation in IPexpress ........................................................................................................................ 27
Getting Started ........................................................................................................................................... 27
Configuring CFR Core in IPexpress........................................................................................................... 28
IPexpress-Created Files and Top Level Directory Structure...................................................................... 30
Instantiating the Core ................................................................................................................................. 31
Running Functional Simulation .................................................................................................................. 31
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 32
Hardware Evaluation.................................................................................................................................. 32
Enabling Hardware Evaluation in Diamond................................................................................................ 32
Updating/Regenerating the IP Core ........................................................................................................... 32
IP Core Generation in Clarity Designer............................................................................................................... 33
Getting Started ........................................................................................................................................... 33
IP Core Implementation ............................................................................................................................. 38
Hardware Evaluation.................................................................................................................................. 39
Enabling Hardware Evaluation in Diamond................................................................................................ 39
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 39
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 40
Chapter 5. Support Resources ............................................................................................................ 41
Lattice Technical Support.................................................................................................................................... 41
E-mail Support ........................................................................................................................................... 41
Local Support ............................................................................................................................................. 41
Internet ....................................................................................................................................................... 41
IEEE ........................................................................................................................................................... 41
References.......................................................................................................................................................... 41
LatticeECP3 ............................................................................................................................................... 41
ECP5.......................................................................................................................................................... 41
©2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or
product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG109_1.1, May 2014
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Peak Cancellation Crest Factor Reduction
IP Core User’s Guide
Chapter 1:
Introduction
Crest Factor Reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such
as those used in third-generation (3G) code division multiple access (CDMA) or long term evolution (LTE) wireless
applications. A power amplifier is used in the final stage of transmitting signal in cellar base stations and is perfor-
mance limited by high PAR. Amplifiers work best in the linear range where input signals stay within a bounded
range. Large peaks in the input signal drive the amplifier into the non-linear region, which can cause adjacent
channel leakage and low power efficiency.
The Lattice Peak Cancellation Crest Factor Reduction (PC-CFR) IP core is flexible and has an efficient implemen-
tation supporting the LatticeECP3 FPGA device families. The highly configurable design takes advantage of the
embedded DSP blocks available in Lattice FPGAs.
Quick Facts
Table 1-1. PC-CFR IP Core Quick Facts
PC-CFR Core Configuration
1 Antenna
1 Stage
8 Clip engines
Core
Requirements
Resource
Utilization
FPGA Families Supported
Minimum Device Required
Width of data
Width of coefficient
Targeted Device
Registers
LUTs
sysMEM EBRs
MULT18X18
Resource
Utilization
Targeted Device
Registers
LUTs
sysMEM EBRs
MULT18X18
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
2988
2704
5
10
2750
2643
5
18
1 Antenna
2 Stages
10 Clip engines
LatticeECP3™, ECP5™
LFE3-35EA, LFE5UM-25F
18
18
LFE3-70EA-9FN672C
4321
4493
7
24
LFE5UM-85F-8MG756C
4672
4537
7
14
Lattice Diamond
®
3.2
Synopsys
®
Synplify™ Pro I-2013.09L
Mentor Graphics
®
ModelSim™ SE Plus 6.3f
Aldec
®
Active-HDL™ 9.3 Lattice Edition
6800
6658
10
20
6338
6599
10
34
1 Antenna
3 Stages
14 Clip engines
IPUG109_1.1, May 2014
4
Peak Cancellation Crest Factor Reduction
IP Core User’s Guide
Introduction
Features
• The Lattice PC-CFR IP supports one to four antennas.
• The core can be configured for clock-to-sample ratios of 1, 2 or 4.
• Provides 1, 2 or 3 sequential detection and cancellation stages to remove peaks.
• Cancellation pulses may be real or complex.
• Supports up to 4 coefficient sets for dynamic switching.
• Dynamically programmable clipping amplitude threshold and peak detector window width.
• Number of clip engines for each filter stage can be independently configured.
• The peak cancellation pulse length is configurable.
• IP provides parallel or TDM (Time-Division Multiplexing) quadrature (I & Q) format for input/output mode.
• Configurable data width.
• Configurable coefficient width.
• Option for output gain.
• Supports DSP high-speed mode for ECP5 devices
Release Information
Peak Cancellation Crest Factor Reduction IP core version 2.0
Last updated May 2014
Device Support
LatticeECP3, ECP5
IPUG109_1.1, May 2014
5
Peak Cancellation Crest Factor Reduction
IP Core User’s Guide
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