2.2.1. Control and Status Interface ..........................................................................................................................8
2.2.2. Input Data Interface .......................................................................................................................................9
2.2.3. Result Interface ..............................................................................................................................................9
2.2.4. DRAM Interface ..............................................................................................................................................9
2.6.2. Input Data Format ........................................................................................................................................11
2.6.3. Output Data Format .....................................................................................................................................12
4. IP Generation and Evaluation .....................................................................................................................................15
4.1.
Licensing the IP ..................................................................................................................................................15
4.2.
Generation and Synthesis .................................................................................................................................15
4.2.1. Getting Started .............................................................................................................................................15
4.2.2. Configuring the IP Core in Clarity .................................................................................................................16
4.2.3. Instantiating the IP Core ...............................................................................................................................16
5. Ordering Part Number ................................................................................................................................................18
Technical Support Assistance .............................................................................................................................................19
Appendix A. Resource Utilization .......................................................................................................................................20
Revision History ..................................................................................................................................................................21
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Figure 2.2. CNN Accelerator IP Core Interface Diagram ....................................................................................................... 6
Figure 2.3. Control and Status Interface Timing Diagram .................................................................................................... 8
Figure 2.4. Input Data Interface Timing Diagram ................................................................................................................. 9
Figure 2.5. Result Interface Timing Diagram ........................................................................................................................ 9
Table 2.1. CNN Accelerator IP Core Signal Descriptions ....................................................................................................... 6
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02037-1.1
3
CNN Accelerator IP Core
User Guide
1. Introduction
The Lattice Semiconductor CNN Accelerator IP Core is a calculation engine for Deep Neural Network with fixed point
weight or binarized weight. It calculates full layers of Neural Network including convolution layer, pooling layer, batch
normalization layer, and full connect layer by executing sequence code with weight value which is generated by Lattice
Neural Network Compiler. The engine is optimized for convolutional neural network, so it can be used for vision-based
application such as classification or object detection and tracking. The IP Core does not require an extra processor; it
can perform all required calculations by itself.
The design is implemented in Verilog HDL. It can be targeted to ECP5 and ECP5-5G FPGA devices, and implemented
using the Lattice Diamond® Software Place and Route tool integrated with the Synplify Pro® synthesis tool.
1.1. Quick Facts
Table 1.1
presents a summary of the CNN Accelerator IP Core.
Table 1.1. Quick Facts
IP Requirements
FPGA Families Supported
Targeted Device
Resource Utilization
Supported User Interface
Resources
Lattice Implementation
Design Tool Support
Synthesis
Simulation
ECP5, ECP5-5G
Full configuration: 85k devices in ECP5 families
Reduced configuration: All devices in ECP5 families
AXI3, Native interfaces as described in
Interface Descriptions
section.
See
Table A.1.
Lattice Diamond Design Suite 3.10
Lattice Synthesis Engine
Synopsys® Synplify Pro, M-2017.03LR-SP1-1
For a list of supported simulators, see the Lattice Diamond User
Guide.
1.2. Features
The key features of the CNN Accelerator IP Core include:
Support for convolution layer, max pooling layer, batch normalization layer, and full connect layer
Configurable bit width of weight (16-bit, 1-bit)
Configurable bit width of activation (16/8-bit, 1-bit)
Dynamic support for 16-bit and 8-bit width of activation
Configurable number of memory blocks for tradeoff between resource and performance
Configurable number of convolution engines for tradeoff between resource and performance
Optimization for 3 x 3 2D convolution calculation
Dynamic support for various 1D convolution from 1 to 72 taps
Support for max pooling with overlap (For example, kernel 3, stride 2)
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
FPGA-IPUG-02037-1.1
CNN Accelerator IP Core
User Guide
2. Functional Descriptions
2.1. Overview
The CNN Accelerator IP Core performs a series of calculations per command sequence that is generated by the Lattice
Neural Network Compiler tool. Commands must be written at DRAM address specified by the i_code_base_addr signal
which is accessible through AXI BUS. Input data may be read from DRAM at a pre-defined address or directly written
through the input data write port. After command code and input data are available, CNN Accelerator IP Core starts
calculation at the rising edge of start signal. During calculation, intermediate data and final result may be transferred to
DRAM or fed out through the result write port. All operations are fully-programmable by command code.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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