MT25QU512ABB8E12-0AUTDC datasheet, PDF

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MT25QU512ABB8E12-0AUTDC: DescriptionNOR flash memory; Categorysemiconductor Memory IC NOR flash memory; File Size1MB，101 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT25QU512ABB8E12-0AUTDC Overview

NOR flash memory

MT25QU512ABB8E12-0AUTDC Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	T-PBGA-24
series	MT25QU
storage	512 Mbit
Interface Type	SPI
organize	64 M x 8
Timing type	Synchronous
Data bus width	8 bit
Supply voltage - min.	2.7 V
Supply voltage - max.	3.6 V
Supply current—max.	35 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 125 C
Encapsulation	Tray
Factory packaging quantity	1122

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512Mb, 1.8V Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

1.8V, Multiple I/O, 4KB, 32KB, 64KB Sector Erase

MT25QU512ABB

Features

• SPI-compatible serial bus interface

• Single and double transfer rate (STR/DTR)

• Clock frequency

– 166 MHz (MAX) for all protocols in STR

– 90 MHz (MAX) for all protocols in DTR

• Dual/quad I/O commands for increased through-

put up to 90 MB/s

• Supported protocols in both STR and DTR

– Extended I/O protocol

– Dual I/O protocol

– Quad I/O protocol

• Execute-in-place (XIP)

• PROGRAM/ERASE SUSPEND operations

• Volatile and nonvolatile configuration settings

• Software reset

• Additional reset pin for selected part numbers

• 3-byte and 4-byte address modes – enable memory

access beyond 128Mb

• Dedicated 64-byte OTP area outside main memory

– Readable and user-lockable

– Permanent lock with PROGRAM OTP command

• Erase capability

– Bulk erase

– Sector erase 64KB uniform granularity

– Subsector erase 4KB, 32KB granularity

• Security and write protection

– Volatile and nonvolatile locking and software

write protection for each 64KB sector

– Nonvolatile configuration locking

– Password protection

– Hardware write protection: nonvolatile bits

(BP[3:0] and TB) define protected area size

– Program/erase protection during power-up

– CRC detects accidental changes to raw data

• Electronic signature

– JEDEC-standard 3-byte signature (BB20h)

– Extended device ID: two additional bytes identify

device factory options

• JESD47H-compliant

– Minimum 100,000 ERASE cycles per sector

– Data retention: 20 years (TYP)

Options

• Voltage

– 1.7–2.0V

• Density

– 512Mb

• Device stacking

– Monolithic

• Device generation

• Die revision

• Pin configuration

– HOLD#

– RESET# and HOLD#

• Sector Size

– 64KB

• Packages – JEDEC-standard, RoHS-

compliant

– 24-ball T-PBGA 05/6mm × 8mm

(TBGA24)

– Wafer level chip-scale package, 27

balls, 9 active balls (XFWLBGA 0.5P)

– 16-pin SOP2, 300 mil

(SO16W, SO16-Wide, SOIC-16)

– W-PDFN-8 8mm × 6mm

(MLP8 8mm × 6mm)

• Security features

– Standard security

• Special options

– Standard

– Automotive

• Operating temperature range

– From –40°C to +85°C

– From –40°C to +105°C

– From –40°C to +125°C

Marking

512

09005aef864f8d6d

mt25q-qlkt-u512-abb-0.pdf - Rev. F 1/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1.8V Multiple I/O Serial Flash Memory

Features

Contents

Important Notes and Warnings ......................................................................................................................... 9

Device Description ......................................................................................................................................... 10

Device Logic Diagram ................................................................................................................................. 11

Advanced Security Protection ..................................................................................................................... 11

Signal Assignments – Package Code: 12 ........................................................................................................... 12

Signal Assignments – Package Code: 56 ........................................................................................................... 13

Signal Assignments – Package Code: SF ........................................................................................................... 14

Signal Assignments – Package Code: W9 .......................................................................................................... 14

Signal Descriptions ......................................................................................................................................... 15

Package Dimensions – Package Code: 12 ......................................................................................................... 17

Package Dimensions – Package Code: 56 ......................................................................................................... 18

Package Dimensions – Package Code: SF ......................................................................................................... 19

Package Dimensions – Package Code: W9 ........................................................................................................ 20

Memory Map – 512Mb Density ....................................................................................................................... 21

Status Register ................................................................................................................................................ 22

Block Protection Settings ............................................................................................................................ 23

Flag Status Register ......................................................................................................................................... 24

Extended Address Register .............................................................................................................................. 25

Internal Configuration Register ....................................................................................................................... 26

Nonvolatile Configuration Register .................................................................................................................. 27

Volatile Configuration Register ........................................................................................................................ 29

Supported Clock Frequencies ..................................................................................................................... 30

Enhanced Volatile Configuration Register ........................................................................................................ 34

Security Registers ........................................................................................................................................... 35

Sector Protection Security Register .................................................................................................................. 36

Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 37

Volatile Lock Bit Security Register .................................................................................................................... 37

Device ID Data ............................................................................................................................................... 38

Serial Flash Discovery Parameter Data ............................................................................................................. 39

Command Definitions .................................................................................................................................... 40

Software RESET Operations ............................................................................................................................ 46

RESET ENABLE and RESET MEMORY Commands ....................................................................................... 46

READ ID Operations ....................................................................................................................................... 47

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 47

READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 48

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 48

READ MEMORY Operations ............................................................................................................................ 49

4-BYTE READ MEMORY Operations ................................................................................................................ 50

READ MEMORY Operations Timings ............................................................................................................... 51

WRITE ENABLE/DISABLE Operations ............................................................................................................. 58

READ REGISTER Operations ........................................................................................................................... 59

WRITE REGISTER Operations ......................................................................................................................... 60

CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 62

PROGRAM Operations .................................................................................................................................... 63

4-BYTE PROGRAM Operations ........................................................................................................................ 64

PROGRAM Operations Timings ....................................................................................................................... 64

ERASE Operations .......................................................................................................................................... 67

SUSPEND/RESUME Operations ..................................................................................................................... 69

PROGRAM/ERASE SUSPEND Operations .................................................................................................... 69

PROGRAM/ERASE RESUME Operations ...................................................................................................... 69

09005aef864f8d6d

mt25q-qlkt-u512-abb-0.pdf - Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1.8V Multiple I/O Serial Flash Memory

Features

ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 71

READ OTP ARRAY Command ...................................................................................................................... 71

PROGRAM OTP ARRAY Command .............................................................................................................. 71

ADDRESS MODE Operations .......................................................................................................................... 73

ENTER and EXIT 4-BYTE ADDRESS MODE Command ................................................................................ 73

DEEP POWER-DOWN Operations ................................................................................................................... 74

ENTER DEEP POWER-DOWN Command .................................................................................................... 74

RELEASE FROM DEEP POWER-DOWN Command ....................................................................................... 74

DEEP POWER-DOWN Timings .................................................................................................................... 75

QUAD PROTOCOL Operations ........................................................................................................................ 77

ENTER or RESET QUAD INPUT/OUTPUT MODE Command ....................................................................... 77

CYCLIC REDUNDANCY CHECK Operations .................................................................................................... 78

State Table ..................................................................................................................................................... 80

XIP Mode ....................................................................................................................................................... 81

Activate and Terminate XIP Using Volatile Configuration Register ................................................................. 81

Activate and Terminate XIP Using Nonvolatile Configuration Register .......................................................... 81

Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 82

Terminating XIP After a Controller and Memory Reset ................................................................................. 82

Power-Up and Power-Down ............................................................................................................................ 83

Power-Up and Power-Down Requirements .................................................................................................. 83

Active, Standby, and Deep Power-Down Modes ................................................................................................ 85

Power Loss and Interface Rescue ..................................................................................................................... 86

Recovery .................................................................................................................................................... 86

Power Loss Recovery ................................................................................................................................... 86

Interface Rescue ......................................................................................................................................... 86

Initial Delivery Status ..................................................................................................................................... 87

Absolute Ratings and Operating Conditions ..................................................................................................... 88

DC Characteristics and Operating Conditions .................................................................................................. 90

AC Characteristics and Operating Conditions .................................................................................................. 92

AC Reset Specifications ................................................................................................................................... 95

Program/Erase Specifications ......................................................................................................................... 99

Revision History ............................................................................................................................................ 100

Rev. F - 1/18 .............................................................................................................................................. 100

Rev. E – 06/17 ............................................................................................................................................ 100

Rev. D – 06/16 ............................................................................................................................................ 100

Rev. C – 06/16 ............................................................................................................................................ 100

Rev. B – 03/16 ............................................................................................................................................ 100

Rev. A – 06/15 ............................................................................................................................................ 100

09005aef864f8d6d

mt25q-qlkt-u512-abb-0.pdf - Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1.8V Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Part Number Ordering Information .................................................................................................... 2

Figure 2: Block Diagram ................................................................................................................................ 10

Figure 3: Logic Diagram ................................................................................................................................. 11

Figure 4: 24-Ball T-BGA, 5 × 5 (Balls Down) ..................................................................................................... 12

Figure 5: 27-Ball XFWLBGA (Top View) .......................................................................................................... 13

Figure 6: 16-Pin, Plastic Small Outline – SO16 (Top View) ................................................................................ 14

Figure 7: 8-Pin, W-PDFN (Top View) .............................................................................................................. 14

Figure 8: 24-Ball T-PBGA (5 × 5 ball grid array) – 6mm × 8mm ......................................................................... 17

Figure 9: 27-Ball XFWLBGA ........................................................................................................................... 18

Figure 10: 16-Pin SOP2 – 300 mil Body Width ................................................................................................. 19

Figure 11: W-PDFN-8 (MLP8) – 8mm × 6mm .................................................................................................. 20

Figure 12: Memory Array Segments ................................................................................................................ 25

Figure 13: Internal Configuration Register ...................................................................................................... 26

Figure 14: Sector and Password Protection ..................................................................................................... 35

Figure 15: RESET ENABLE and RESET MEMORY Command ........................................................................... 46

Figure 16: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 47

Figure 17: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 48

Figure 18: READ – 03h/13h

........................................................................................................................... 51

Figure 19: FAST READ – 0Bh/0Ch

................................................................................................................. 51

Figure 20: DUAL OUTPUT FAST READ – 3Bh/3Ch

......................................................................................... 52

Figure 21: DUAL INPUT/OUTPUT FAST READ – BBh/BCh

............................................................................ 52

Figure 22: QUAD OUTPUT FAST READ – 6Bh/6Ch

........................................................................................ 53

Figure 23: QUAD INPUT/OUTPUT FAST READ – EBh/ECh

............................................................................ 53

Figure 24: QUAD INPUT/OUTPUT WORD READ – E7h

................................................................................. 54

Figure 25: DTR FAST READ – 0Dh/0Eh

.......................................................................................................... 55

Figure 26: DTR DUAL OUTPUT FAST READ – 3Dh

........................................................................................ 55

Figure 27: DTR DUAL INPUT/OUTPUT FAST READ – BDh

............................................................................ 56

Figure 28: DTR QUAD OUTPUT FAST READ – 6Dh

........................................................................................ 57

Figure 29: DTR QUAD INPUT/OUTPUT FAST READ – EDh

............................................................................ 57

Figure 30: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 58

Figure 31: READ REGISTER Timing ................................................................................................................ 59

Figure 32: WRITE REGISTER Timing .............................................................................................................. 61

Figure 33: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 62

Figure 34: PAGE PROGRAM Command .......................................................................................................... 64

Figure 35: DUAL INPUT FAST PROGRAM Command ...................................................................................... 65

Figure 36: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 65

Figure 37: QUAD INPUT FAST PROGRAM Command ..................................................................................... 66

Figure 38: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 66

Figure 39: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 68

Figure 40: BULK ERASE Timing ...................................................................................................................... 68

Figure 41: PROGRAM/ERASE SUSPEND and RESUME Timing ........................................................................ 70

Figure 42: READ OTP Command Timing ........................................................................................................ 71

Figure 43: PROGRAM OTP Command Timing ................................................................................................. 72

Figure 44: ENTER DEEP POWER-DOWN Timing ............................................................................................. 75

Figure 45: RELEASE FROM DEEP POWER-DOWN Timing ............................................................................... 76

Figure 46: XIP Mode Directly After Power-On .................................................................................................. 81

Figure 47: Power-Up Timing .......................................................................................................................... 84

Figure 48: AC Timing Input/Output Reference Levels ...................................................................................... 89

Figure 49: Reset AC Timing During PROGRAM and ERASE Cycle ..................................................................... 96

Figure 50: Reset Enable and Reset Memory Timing ......................................................................................... 96

09005aef864f8d6d

mt25q-qlkt-u512-abb-0.pdf - Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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