CY15B101N
1-Mbit (64K × 16) Automotive F-RAM Memory
1-Mbit (64K × 16) Automotive F-RAM Memory
Features
■
■
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44-pin thin small outline package (TSOP) Type II
Restriction of hazardous substances (RoHS)-compliant
1-Mbit ferroelectric random access memory (F-RAM™)
logically organized as 64K × 16
❐
Configurable as 128K × 8 using UB and LB
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (see the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Page-mode operation for 30-ns cycle time
❐
Advanced high-reliability ferroelectric process
SRAM compatible
❐
Industry-standard 64K × 16 SRAM pinout
❐
60-ns access time, 90-ns cycle time
Superior to battery-backed SRAM modules
❐
No battery concerns
❐
Monolithic reliability
❐
True surface-mount solution, no rework steps
❐
Superior for moisture, shock, and vibration
Low power consumption
❐
Active current 7 mA (typ)
❐
Standby current 120
A
(typ)
Low-voltage operation: V
DD
= 2.0 V to 3.6 V
Automotive-A temperature: –40
C
to +85
C
Functional Description
The CY15B101N is a 64K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write-timing and high
write-endurance make the F-RAM superior to other types of
memory.
The CY15B101N operation is similar to that of other RAM
devices, and, therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the CY15B101N ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil, 44-pin TSOP-II
surface-mount package. Device specifications are guaranteed
over the Automotive-A temperature range –40 °C to +85 °C.
For a complete list of related resources,
click here.
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Logic Block Diagram
Address Latch & Write Protect
Block & Row Decoder
A15-0
A 1-0
...
A 15-2
64K x 16 block
F-RAM Array
CE
WE
UB, LB
OE
ZZ
Control
Logic
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation
Document Number: 001-96058 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 16, 2018
CY15B101N
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Precharge Operation ................................................... 4
Sleep Mode ................................................................. 5
SRAM Drop-In Replacement ....................................... 5
Endurance ................................................................... 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Data Retention and Endurance ....................................... 7
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Conditions .......................................................... 7
AC Switching Characteristics ......................................... 8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle ....................................................... 9
Power Cycle and Sleep Mode Timing ........................... 13
Functional Truth Table ................................................... 14
Byte Select Truth Table .................................................. 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagram ............................................................ 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 001-96058 Rev. *E
Page 2 of 19
CY15B101N
Pinout
Figure 1. 44-Pin TSOP II Pinout
A
4
A
3
A
2
A
1
A
0
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
DD
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
V
SS
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
DD
DQ
11
DQ
10
DQ
9
DQ
8
ZZ
A
8
A
9
A
10
A
11
NC
44-pin TSOP II
(× 16)
Top View
(not to scale)
Pin Definitions
Pin Name
A
0
–A
15
I/O Type
Input
Description
Address inputs:
The 16 address lines select one of 64K words in the F-RAM array. The lowest two
address lines A
1
–A
0
may be used for page mode read and write operations.
Write Enable:
A write cycle begins when WE is asserted. The rising edge causes the CY15B101N to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
Chip Enable:
The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A
1
–A
0
address inputs allow
page mode operation.
Output Enable:
When OE is LOW, the CY15B101N drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
Upper Byte Select:
Enables DQ
15
–DQ
8
pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128K × 8, the UB and LB
pins may be tied to ground.
Lower Byte Select:
Enables DQ
7
–DQ
0
pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128 K × 8, the UB and LB
pins may be tied to ground.
Sleep:
When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to V
DD
if not used.
Ground for the device. Must be connected to the ground of the system.
No connect. This pin is not connected to the die.
DQ
0
–DQ
15
Input/Output
Data I/O Lines:
16-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
CE
Input
OE
UB
Input
Input
LB
Input
ZZ
V
SS
V
DD
NC
Input
Ground
No connect
Power supply Power supply input to the device.
Document Number: 001-96058 Rev. *E
Page 3 of 19
CY15B101N
Device Operation
The CY15B101N is a word-wide F-RAM memory logically
organized as 65,536 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers
page-mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A
15
–A
2
) changes. See the
Functional Truth Table on page 14
for a complete description of read and write modes.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
CY15B101N will not drive the data bus regardless of the state of
OE as long as WE is LOW. Input data must be valid when CE is
deasserted HIGH. In a WE-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown on the
page 10
and
page 11.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Memory Operation
Users access 65,536 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 2048 rows. Each row has four column
locations, which allow fast access in page-mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted (HIGH), a precharge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
“NoDelay” writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is t
RC
. Note that unlike SRAMs,
the CY15B101N's CE-initiated access time is faster than the
address access time.
The CY15B101N will drive the data bus when OE and at least
one of the byte enables (UB, LB) is asserted LOW. The upper
data byte is driven when UB is LOW, and the lower data byte is
driven when LB is LOW. If OE is asserted after the memory
access time is met, the data bus will be driven with valid data. If
OE is asserted before completing the memory access, the data
bus will not be driven until valid data is available. This feature
minimizes the supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Page Mode Operation
The F-RAM array is organized as eight blocks, each having 2048
rows. Each row has four column-address locations. Address
inputs A
1
–A
0
define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A
1
–A
0
may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
t
AAP
, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Precharge Operation
The precharge operation is an internal condition in which the
memory state is prepared for a new access. Precharge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum precharge time, t
PC
.
Precharge is also activated by changing the upper addresses,
A
15
–A
2
. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a precharge operation. The new address is
latched and the new read data is valid within the t
AA
address
access time; see
Figure 5 on page 10.
A similar sequence occurs
for write cycles; see
Figure 10 on page 11.
The rate at which
random addresses can be issued is t
RC
and t
WC
, respectively.
Write Operation
In the CY15B101N, writes occur in the same interval as reads.
The CY15B101N supports both CE- and WE-controlled write
cycles. In both cases, the address A
15
–A
2
is latched on the
falling edge of CE.
Document Number: 001-96058 Rev. *E
Page 4 of 19
CY15B101N
Sleep Mode
The device incorporates a sleep mode of operation, which allows
the user to achieve the lowest-power-supply-current condition. It
enters a low-power sleep mode by asserting the ZZ pin LOW.
Read and write operations must complete before the ZZ pin
going LOW. When ZZ is LOW, all pins are ignored except the ZZ
pin. When ZZ is deasserted HIGH, there is some time delay
(t
ZZEX
) before the user can access the device.
If sleep mode is not used, the ZZ pin must be tied to V
DD
.
Figure 2. Sleep/Standby State Diagram
Power
Applied
CE HIGH,
ZZ HIGH
Standby
ZZ LOW
Initialize
CE LOW,
ZZ HIGH
Normal
Operation
ZZ LOW
ZZ HIGH
A
16
A
15-0
CE
WE
OE
ZZ
For applications that require the lowest power consumption, the
CE signal should be active (LOW) only during memory accesses.
The CY15B101N draws supply current while CE is LOW, even if
addresses and control signals are static. While CE is HIGH, the
device draws no more than the maximum standby current, I
SB
.
The UB and LB byte select pins are active for both read and write
cycles. They may be used to allow the device to be wired as a
128K × 8 memory. The upper and lower data bytes can be tied
together and controlled with the byte selects. Individual byte
enables or the next higher address line A
16
may be available
from the system processor.
Figure 4. CY15B101N Wired as 128 K x 8
CE LOW,
ZZ HIGH
CE HIGH,
ZZ HIGH
Sleep
1-Mbit F-RAM
CY15B101N
DQ
15-8
D
DQ
7-0
7-0
UB
LB
A
15-0
Endurance
SRAM Drop-In Replacement
The CY15B101N is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require CE
to toggle for each new address. CE may remain LOW indefinitely.
While CE is LOW, the device automatically detects address
changes and a new access begins. This functionality allows CE
to be grounded, similar to an SRAM. It also allows page mode
operation at speeds up to 33 MHz. Note that if CE is tied to
ground, the user must be sure WE is not LOW at power-up or
power-down events. If CE and WE are both LOW during power
cycles, data will be corrupted.
Figure 3
shows a pull-up resistor
on WE, which will keep the pin HIGH during power cycles,
assuming the MCU/MPU pin tristates during the reset condition.
The pull-up resistor value should be chosen to ensure the WE
pin tracks V
DD
to a high enough value, so that the current drawn
when WE is LOW is not an issue. A 10-k resistor draws 330 µA
when WE is LOW and V
DD
= 3.3 V.
Figure 3. Use of Pull-up Resistor on WE
VDD
CY15B101N
CE
WE
The CY15B101N is capable of being accessed at least 10
14
times – reads or writes. An F-RAM memory operates with a read
and restore mechanism. Therefore, an endurance cycle is
applied on a row basis. The F-RAM architecture is based on an
array of rows and columns. Rows are defined by A
15-2
and
column addresses by A
1-0
. The array is organized as 16K rows
of four words each. The entire row is internally accessed once
whether a single 16-bit word or all four words are read or written.
Each word in the row is counted only once in an endurance
calculation.
The user may choose to write CPU instructions and run them
from a certain address space.
Table 1
shows endurance
calculations for a 256-byte repeating loop, which includes a
starting address, three-page mode accesses, and a CE
precharge. The number of bus clock cycles needed to complete
a four-word transaction is 4 + 1 at lower bus speeds, but 5 + 2 at
33 MHz due to initial read latency and an extra clock cycle to
satisfy the device's precharge timing constraint t
PC
. The entire
loop causes each byte to experience only one endurance cycle.
The F-RAM read and write endurance is virtually unlimited even
at a 33-MHz system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating
256-byte Loop
Bus
Freq
(MHz)
33
25
10
5
Bus
256-byte
Endurance Endurance
Cycle
Transaction
Cycles/sec Cycles/year
Time
Time (s)
(ns)
30
40
100
200
10.56
12.8
28.8
57.6
94,690
78,125
34,720
17,360
2.98 x 10
12
2.46 x 10
12
1.09 x 10
12
MCU / MPU
OE
A
15-0
DQ
15-0
Years to
Reach
10
14
Cycles
33.5
40.6
91.7
182.8
5.47 x 10
11
Document Number: 001-96058 Rev. *E
Page 5 of 19
Test/Measurement
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