S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit
TM
Flash Memory & DRAM
128 Mb (8 M x 16 bit)/256 Mb (16 M x 16 bit),
110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write,
Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR
DRAM
Data Sheet
ADVANCE
INFORMATION
Notice to Readers:
The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number
S72NS128_256ND0_00
Revision
B
Amendment
1
Issue Date
November 9, 2005
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
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cific products, but has not committed any design to production. Information presented in a
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uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
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changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V
IO
range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
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sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S72NS128/256ND0 Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
S72NS-N Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit
TM
Flash Memory & DRAM
128/256 Mb (8/16 M x 16 bit), 110nm CMOS 1.8 Volt-only,
Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory
and 128/256-Mb (8/16-M x 16-bit) DDR DRAM
Data Sheet
ADVANCE
INFORMATION
General Description
This document contains information on the S72NS-N MCP product family. Refer to the S29NS-N
data sheet (S29NS256/128N_01, revision A4) for full electrical specifications of the Flash memory
component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifica-
tions of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0)
for full electrical specifications of the DDR SDRAM component
The S72NS Series is a product line of stacked Multi-Chip Product (MCP) products and consists of:
One or more NS family multiplexed Flash memory die
DDR DRAM
The products covered by this document are listed in the table below.
DRAM Density
Flash Density
128 Mb
256 Mb
512 Mb
128 Mb
S72NS128ND0
S72NS256ND0
S72NS512ND0
S72NS512NE0
256 Mb
S72NS256ND0
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V
Burst Speeds
— Flash = 66 MHz, 80 MHz
— DRAM = 133 MHz
Packages, 133-ball FBGA
— 11.0 x 10.0 x 1.0 mm
— 8.0 x 8.0 x 1.0 mm
Operating Temperature of 25°C to +85°C
Product Selector Guide
Device- Model#
S72NS256ND0-7K
S72NS256ND0-7J
S72NS256ND0-73
S72NS256ND0-72
S72NS128ND0-1K
S72NS128ND0-1J
S72NS128ND0-13
S72NS128ND0-12
S72NS512ND0-7K
S72NS512ND0-7J
S72NS512ND0-73
S72NS512ND0-72
S72NS512NE0-7K
S72NS512NE0-7J
S72NS512NE0-73
S72NS512NE0-72
512 Mb
256 Mb
512 Mb
128 Mb
128 Mb
128 Mb
256 Mb
128 Mb
Flash Density
DRAM Density
Flash Speed (MHz)
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
133
133
DRAM Speed (MHz)
Supplier
DRAM
Type 1
DRAM
Type 5
DRAM
Type 1
DRAM
Type 5
DRAM
Type 1
DRAM
Type 5
DRAM
Type 1
DRAM
Type 5
MTA133
11x10mm
Package
NLC133,
11x10mm
NLE133,
8x8mm
Publication Number
S72NS128_256ND0_00
Revision
B
Amendment
1
Issue Date
November 9, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Contents
1
2
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 256 Mb Flash + 128 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 512 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 512 Mb Flash + 256 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 128 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA)
11.0 x 10.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5.2 NLE133—133-ball Fine-Pitch Ball Grid Array (FBGA)
8.0 x 8.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 MTA133—133-ball Fine-Pitch Ball Grid Array (FBGA)
10.0 x 11.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
5
6
2
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e
I n f o r m a t i o n
1
MCP Block Diagrams
F-RST#
F-V
PP
F-WP#
F-CE#
F-OE#
F-WE#
AVD#
F-V
SS
F2-CE#
RST#
V
PP
WP#
CE#
OE#
WE#
AVD#
V
SS
A15-A0
DQ15-DQ0
ADQ15-ADQ0
MUX
Flash
Memory
NS-N
CLK
RDY
F-CLK
F-RDY
A16-Amax
V
CC
V
CCQ
A16-Amax
F-V
CC
F-V
CCQ
Second NS-N (if needed)
D-RAS#
D-CAS#
D-BA0
D-BA1
D-CKE
D-WE#
D-Amax - D-A0
D-V
CC
D-V
CCQ
V
CC
V
CCQ
(Note
3)
RAS#
CAS#
BA0
BA1
CKE
WE#
CLK
CLK#
DQS0
DQS1
LDQM
UDQM
TEST
DQ15-DQ0
V
SS
V
SSQ
D-CLK
D-CLK#
D-LDQS
D-UDQS
D-LDQM
D-UDQM
D-TEST
D-DQ15 - D-DQ0
D-V
SS
D-V
SSQ
DDR
DRAM
Memory
Notes:
1.
2.
3.
Amax indicates highest address bit for memory component:
a. Amax = A23 for NS256N, A22 for NS128N
b. Amax = A11 for 128 Mb DDR DRAM, A12 for 256-Mb DDR DRAM
For Flash, A0 – A15 is tied to DQ0 – DQ15.
For the NS512N, two NS-N devices are included. All signals are common to both except for CE#. F-CE# becomes F1-CE#, while the CE#
for the second flash is F2-CE#. This way, the two NS-N devices are separately accessed.
Figure 1.1.
MCP Block Diagram
November 9, 2005 S72NS128_256ND0_00_B1
S72NS-N Based MCPs
3
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