Intelligent Frequency Synthesizers
Preliminary Data Sheet
FEATURES:
∗
DESCRIPTION:
PNP-1050-L22
The PNP-1050-L22 is a complete low noise frequency syn-
thesizer, comprised of VCO, PLL, loop filter and data inter-
face. The PNP family of RF signal sources is the world’s
first truly configurable frequency synthesizer module. PNP
technology offers the designer the ability to configure all of
the synthesizer’s vital functions ‘on the fly’ with simple
strings of code that contain the commands of START,
STOP, STEP, CHANNEL and REF. When new data is re-
ceived, the PNP module optimizes its internal settings for
best overall integrated phase noise, switching speed and
spurious suppression, all automatically and in less than 100
µS.
Therefore, if the system requires 100 kHz steps in
mode #1 and 1 MHz step size in mode #2, these smart syn-
thesizers can make quick adjustments with amazing accu-
racy, speed and performance.
Control of the internal registers is accomplished through a
serial data interface. Many industry standard protocols are
supported, including I
2
C, SPI, and MICROWIRE Serial In-
terfaces. The PNP-1050-L22 is powered from a +3V and
+5V supply while dissipating less than 175 mW.
1000-1100 MHz Frequency
Range
∗
Programmable Step Size
∗
Low Integrated Phase Noise
∗
Simplified Programming
APPLICATIONS:
∗
∗
∗
Wireless Infrastructure
Test Equipment
Wireless LAN
MICROWIRE is a trademark of National Semiconductor Corp.
SPI is a trademark of Motorola, Inc.
I
2
C is a trademark of Philips Corp.
Package Drawing
TOP
0.000
0.050
0.130
0.210
0.290
0.370
0.450
0.500
all dimensions in inches
SIDE
GND
GND
BOTTOM
GND
GND
GND
GND
DA0
DA1
DA2
LD
N/C
GND
0.500
0.410
0.330
0.250
0.170
0.090
0.000
0.000
0.050
0.130
0.210
0.290
0.450
0.500
0.370
0.500
UMC
0.410
0.330
GND
REF
V2
V1
RF
PNP-1050-L22
1000-1100 MHz
0.250
0.170
7-03
0.090
0.000
0.000
0.180
GND
GND
GND
Universal Microwave Corporation, 2339 Destiny Way, Odessa, FL 33556
UMC Worldwide Customer Support Center: 4703 S. Lakeshore Drive, Suite 2, Tempe, AZ 85282
1.877.UMC.Xtreme / Fax 480.756.6026
GND
GND
Pin Descriptions
Mnemonic
RF
V1
V2
REF
PNP-1050-L22
FUNCTION
RF Output. This pin is AC coupled and should be connected to a non-reflective 50 ohm load.
Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin.
Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin.
Reference Input. This is a CMOS input with a nominal threshold of V
2
/2 and a dc equivalent
input resistance of 100K ohms. This input can be driven from a CMOS or TTL crystal clock
oscillator or it can be ac coupled.
Digital, Analog and RF Ground.
Serial Interface. This input functions as
CS
in MICROWIRE/SPI Bus mode. This input func-
tions as
SDA
in I
2
C BUS mode.
Serial Interface. This input functions as
DATA
in MICROWIRE/SPI BUS mode. This input
functions as
SCL
in I
2
C BUS mode.
Serial Interface. This input functions as
CLOCK
in MICROWIRE/SPI BUS mode. This input
must be connected to the
GROUND
in I
2
C BUS mode.
Lock Detect. This output is active high and provides a continuous digital lock status.
GND
DA0
DA1
DA2
LD
Absolute Maximum Ratings
V1 to Ground
V2 to Ground
REF IN to Ground
RF OUT to Ground
Digital I/O to Ground
-0.3 to +5.5 V
dc
-0.3 to +3.6 V
dc
-0.3 to (D
vdd
+ 0.3) V
dc
+/- 25 V
dc
-0.3 to V
2
+ 0.3 V
dc
Stress above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress
rating only. Operation of the device above the conditions listed
in the operational sections of this specification is not implied.
Operating Temperature
Storage Temperature
-40
°
to +85
°
C
-55
°
to +100
°
C
Ordering Guide
Model
PNP-1050-L22
PNP-1050A-L22
PNP-1050B-L22
PNP-1050C-L22
CAUTION!
PNP-1050-L22
I
2
C Address
Default
Default + 1
Default + 2
Default + 3
Type Code
P001
P001
P001
P001
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as
4000V readily accumulate on the human body and test equipment and can dis-
charge without detection. Although the PNP family of synthesizers feature ESD
protection circuitry, permanent damage may occur on devices subjected to high-
energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality
Digital Interface
PNP-1050-L22
Bus for control of the PNP synthesizer module, the DA2
line (see Package Drawing, Page 1) must be tied to Digi-
tal Ground. Additionally, the SDA and SCL lines must be
pulled up to D
vdd
using external resistors.
Multiple PNP devices can reside on the same two wire
Bus without the danger of corrupted data or data colli-
sions. Device selection is accomplished by sending a
slave address preceding each string of data. If only one
PNP device will be used on the I
2
C Bus, then the factory
pre-set base address will operate properly. If more than
one PNP device will reside on the same I
2
C Bus, then
modules with unique address locations must be used.
This should be specified when ordering (see Ordering
Guide on page 3). For additional information refer to the
I
2
C Bus specification (copyright Philips Corp).
Overview
The PNP family of intelligent Frequency Synthesizers can
be controlled through the use of a microprocessor inter-
face or Bus. Several protocols are supported by PNP
devices, although this specification will focus on SPI Bus,
MICROWIRE-Interface and I
2
C Bus implementations.
For SPI and MICROWIRE applications, PNP devices re-
quire a single 32 bit string of serial data to set frequency
or to change its internal settings (Figure 1). I
2
C Bus util-
izes some unique control bits and requires the addition of
an ADDRESS byte, increasing the serial bit-stream for
this protocol to 47 bits per command (Figure 2).
The PNP device is programmed at the factory with pre-
sets for the START, STOP, STEP and REFERENCE
registers. It is not necessary to re-load any of these reg-
isters if the factory values are acceptable. If the applica-
tion requires different values than the factory pre-sets,
then the PNP device must first be initialized by loading
data into each of the affected registers. It is not neces-
sary to re-load any registers that are already set properly
for the application. START defines the lowest desired
frequency of operation. STOP defines the highest de-
sired frequency of operation. STEP is used to channelize
the band and REFERENCE defines the frequency of the
external reference. Once the PNP device is initialized, a
fixed number channels are available. Loading the CHAN-
NEL register sets the operating frequency of the PNP
device. The formula for calculating the operating fre-
quency is:
START(Hz) + (CHANNEL * STEP(Hz)) = Frequency(Hz)
I
2
C Implementation
Transferring data to PNP synthesizers using I
2
C protocol
varies significantly from that of SPI or MICROWIRE.
PNP modules operate as slaves on the I
2
C Bus and do
not write to the Bus. However, due to the fact that many
devices might reside on the same Bus, addressing must
be used to direct the flow of data traffic. So, within the bit
stream sent to the PNP device, there is a block of data
that comprises the ADDRESS byte. Within this address
byte there are 7 bits that are used for the address loca-
tion and the eighth is used as a read/write (R/W) bit.
Since PNPs are slaves and will never write to the I
2
C
Bus, this bit will always be set to 0 (logic low).
Each data string is sent using a series of five single byte
blocks. I
2
C protocol requires that each string of data be-
gin with a master generated START (S). Each byte
within the string must end with a slave generated AC-
KNOWLEDGE (A). Finally, after all five bytes are gener-
ated, the transfer is concluded with a master generated
STOP (P). The master generated STOP must be exe-
cuted following each data string for the values to be ac-
cepted by the PNP device. If this condition is not satis-
fied and a new master generated START occurs, the
PNP device will purge the previous data without updating
the desired attribute. REPEATED START (S
r
) operation
is not allowed when sending data to the PNP device.
The flow of data bytes to the PNP device is outlined in
Figure 2. Since FUNCTION SELECT and MULTIPLIER
are 4 bits each, these blocks of data are combined into
one byte. Additionally, since the FREQUENCY/
CHANNEL block of data is 24 bits long, it must be frag-
mented into three individual bytes as shown.
MICROWIRE Interface and SPI Bus
MICROWIRE-Interface and SPI Bus are extremely similar
protocols (Figures 6 & 7). DATA bits are clocked into
the PNP device on the rising edge of the CLOCK input.
CS, or chip select not, must be in a low state for the in-
coming DATA bits to be accepted. After all 32 bits have
been clocked in, the CS line must transition high for the
DATA string to be latched. After the string is latched, the
information in the FUNCTION block (Figure 5) deter-
mines where the data will be routed internally.
I
2
C Bus
The I
2
C Bus is a high-speed method of communicating
over a two wire interface. PNP modules are configured
as “slaves” or receive-only devices and can only listen for
commands from the “master” which is typically a micro-
processor. The I
2
C two wire Bus consists of SDA (serial
data) and SCL (serial clock) lines. In order to use the I
2
C
MCU
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