S71WS512NE0BFWZZ
Stacked Multi-Chip Product (MCP) Flash Memory
and pSRAM CMOS 1.8 Volt,
Simultaneous Operation, Burst Mode Flash Memory
and Pseudo-Static RAM
ADVANCE
INFORMATION
DISTINCTIVE CHARACTERISTICS
MCP Features
Operating Voltage Range of 1.65 to 1.95 V
High Performance
— Speed: 54MHz
Packages
— 96-ball FBGA—9 x 12 mm
Operating Temperatures
— Wireless: –25°C to +85°C
GENERAL DESCRIPTION
The S71WS512 Series is a product line of stacked Multi-Chip
Products (MCP) and consists of
One or more S29WS256N
(Simultaneous Operation, Burst Mode) Flash Die
pSRAM options
— 128Mb pSRAM
The products covered by this document are listed below. For
details about their specifications, please refer to the individual
constituent data sheets for further details.
Number of S29WSxxxN
2
Total Flash Density
512Mb
pSRAM Density
256Mb
MCP
S71WS512NE0
Notes:
1. This MCP is only guaranteed to operate @ 1.65 - 1.95 V regardless of component operating ranges.
Publication Number
S71WS512NE0BFWZZ_00
Revision
A
Amendment
1
Issue Date
June 28, 2004
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
Device-Model #
S71WS512NE0BFWZZ
SRAM/pSRAM Density
256Mb
SRAM/pSRAM Type
pSRAM - x16
Supplier
COSMORAM 1
Flash Access RAM Access
Time (MHz) Time (MHz)
54
54
Packages
TBD
2
S71WS512NE0BFWZZ
S71WS512NE0BFWZZ_00_A1 June 28, 2004
A d v a n c e
I n f o r m a t i o n
TABLE OF CONTENTS
S71WS512NE0BFWZZ
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram of S71WS512NE0BFWZZ ...........................................6
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode .............................................................................................33
Lock Register ....................................................................................................... 34
Table 6. Lock Register ........................................................ 34
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagram of S71WS512NE0BFWZZ ..........................................7
Special Package Handling Instructions ........................................................8
Pin Description ..................................................................................................8
Logic Symbol .....................................................................................................9
Device Bus Operation ....................................................................................... 10
Table 1. Device Bus Operations ........................................... 10
Pin Capacitance ................................................................................................... 12
Physical Dimensions TBD . . . . . . . . . . . . . . . . . . 13
XXX .........................................................................................................................13
Hardware Data Protection Mode ................................................................. 34
Write Protect (WP#) ................................................................................... 34
Low V
CC
Write Inhibit ................................................................................. 34
Write Pulse “Glitch” Protection ............................................................... 35
Logical Inhibit ................................................................................................... 35
Power-Up Write Inhibit ............................................................................... 35
Standby Mode ...................................................................................................... 35
Automatic Sleep Mode ..................................................................................... 35
RESET#: Hardware Reset Input ................................................................ 35
Output Disable Mode ................................................................................... 36
SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 36
Factory Locked: Factor SecSi Sector Programmed and Protected At
the Factory ....................................................................................................... 36
Table 7. SecSi
TM
Sector Addresses ........................................ 37
S29WSxxxN MirrorBit™ Flash Family
For Multi-chip Products (MCP)
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 14
General Description . . . . . . . . . . . . . . . . . . . . . . . . 16
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 19
Block Diagram .................................................................................................... 19
Customer SecSi Sector ................................................................................. 37
SecSi Sector Protection Bit ......................................................................... 37
Common Flash Memory Interface (CFI) . . . . . . 37
Table 8. CFI Query Identification String ................................ 38
Table 9. System Interface String ......................................... 38
Table 10. Device Geometry Definition ................................... 39
Table 11. Primary Vendor-Specific Extended Query ................ 39
Table 12. Sector Address / Memory Address Map for the WS256N
........................................................................................ 41
Block Diagram of Simultaneous Operation Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 21
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. Device Bus Operations ........................................... 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 49
Reading Array Data ...........................................................................................49
Set Configuration Register Command Sequence .....................................49
Read Configuration Register Command Sequence ..................................50
Figure 1. Synchronous/Asynchronous State Diagram.............. 50
Requirements for Asynchronous Read Operation (Non-Burst) ..........23
Requirements for Synchronous (Burst) Read Operation ...................... 24
Table 3. Address Dependent Additional Latency ..................... 24
Read Mode Setting .........................................................................................50
Programmable Wait State Configuration ...............................................50
Table 13. Programmable Wait State Settings ......................... 51
Continuous Burst ........................................................................................... 24
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................25
Table 4. Burst Address Groups ............................................ 25
Programmable Wait State ............................................................................ 51
Boundary Crossing Latency ......................................................................... 51
Set Internal Clock Frequency ...................................................................... 51
Table 14. Wait States for Handshaking ................................. 51
8-, 16-, and 32-Word Linear Burst without Wrap Around ................25
Configuration Register ......................................................................................25
Handshaking ..........................................................................................................25
Simultaneous Read/Write Operations with Zero Latency ................... 26
Writing Commands/Command Sequences ................................................ 26
Unlock Bypass Mode .................................................................................... 26
Accelerated Program/Erase Operations ..................................................... 26
Write Buffer Programming Operation .........................................................27
Autoselect Mode ................................................................................................ 28
Advanced Sector Protection and Unprotection ....................................... 29
Persistent Mode Lock Bit ............................................................................ 29
Password Mode Lock Bit ............................................................................. 30
Sector Protection ............................................................................................... 30
Persistent Sector Protection .......................................................................... 30
Persistent Protection Bit (PPB) ...................................................................31
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ..............................................................................................31
Dynamic Protection Bit (DYB) ....................................................................31
Table 5. Sector Protection Schemes ..................................... 32
Handshaking ...................................................................................................... 51
Burst Sequence ............................................................................................... 52
Burst Length Configuration ......................................................................... 52
Table 15. Burst Length Configuration ................................... 52
Burst Wrap Around ...................................................................................... 52
Burst Active Clock Edge Configuration .................................................. 52
RDY Configuration ........................................................................................ 52
RDY Polarity .................................................................................................... 52
Configuration Register ...................................................................................... 53
Table 16. Configuration Register .......................................... 53
Reset Command ................................................................................................. 53
Autoselect Command Sequence .................................................................... 54
Table 17. Autoselect Addresses ........................................... 54
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 55
Word Program Command Sequence ........................................................... 55
Write Buffer Programming Command Sequence ..................................... 56
Table 18. Write Buffer Command Sequence .......................... 56
Figure 2. Write Buffer Programming Operation ...................... 57
Password Sector Protection ............................................................................33
64-bit Password ...............................................................................................33
Unlock Bypass Command Sequence ........................................................ 57
Figure 3. Program Operation ............................................... 58
June 28, 2004 S71WS512NE0BFWZZ_00_A1
3
A d v a n c e
I n f o r m a t i o n
Chip Erase Command Sequence ................................................................... 58
Sector Erase Command Sequence .................................................................59
Erase Suspend/Erase Resume Commands .................................................. 60
Figure 4. Erase Operation.................................................... 61
Program Suspend/Program Resume Commands ...................................... 61
Lock Register Command Set Definitions ................................................... 62
Password Protection Command Set Definitions ..................................... 62
Non-Volatile Sector Protection Command Set Definitions ..................63
Global Volatile Sector Protection Freeze Command Set ..................... 64
Volatile Sector Protection Command Set ...................................................65
SecSi Sector Entry Command .........................................................................65
Command Definition Summary ..................................................................... 66
Write Operation Status . . . . . . . . . . . . . . . . . . . . .69
DQ7: Data# Polling ........................................................................................... 69
Figure 5. Data# Polling Algorithm......................................... 70
Figure 22. Synchronous Program Operation Timings: CLK Latched
Addresses......................................................................... 88
Figure 23. Accelerated Unlock Bypass Programming Timing..... 88
Figure 24. Data# Polling Timings (During Embedded Algorithm) ...
........................................................................................ 89
Figure 25. Toggle Bit Timings (During Embedded Algorithm) ... 89
Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings ..
........................................................................................ 90
Figure 27. DQ2 vs. DQ6 ..................................................... 90
Figure 28. Latency with Boundary Crossing when Frequency > 66
MHz................................................................................. 91
Figure 29. Latency with Boundary Crossing into Program/Erase
Bank................................................................................ 91
Figure 30. Example of Wait States Insertion.......................... 92
Figure 31. Back-to-Back Read/Write Cycle Timings ................ 92
Erase and Programming Performance . . . . . . . . 93
RDY: Ready .......................................................................................................... 70
DQ6: Toggle Bit I ............................................................................................... 70
Figure 6. Toggle Bit Algorithm.............................................. 71
128Mb pSRAM
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FUNCTION TRUTH TABLE . . . . . . . . . . . . . . . 95
Asynchronous Operation (Page Mode) ..................................................... 95
DQ2: Toggle Bit II ...............................................................................................72
Table 19. DQ6 and DQ2 Indications ..................................... 72
Reading Toggle Bits DQ6/DQ2 ......................................................................72
DQ5: Exceeded Timing Limits ........................................................................73
DQ3: Sector Erase Timer .................................................................................73
DQ1: Write to Buffer Abort ............................................................................73
Table 20. Write Operation Status ......................................... 74
FUNCTION TRUTH TABLE (Continued) . . . . 96
Synchronous Operation (Burst Mode) .......................................................96
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 75
Figure 7. Maximum Negative Overshoot Waveform................. 75
Figure 8. Maximum Positive Overshoot Waveform .................. 75
STATE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 97
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 98
Power-up ...............................................................................................................98
Configuration Register ......................................................................................98
CR Set Sequence ................................................................................................98
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76
CMOS Compatible .............................................................................................76
Test Conditions ...................................................................................................77
Figure 9. Test Setup ........................................................... 77
Table 21. Test Specifications ............................................... 77
FUNCTIONAL DESCRIPTION (Continued) . . 99
Address Key .........................................................................................................99
FUNCTIONAL DESCRIPTION (Continued) . 100
Power Down ...................................................................................................... 100
FUNCTIONAL DESCRIPTION (Continued) . . 101
Burst Read/Write Operation ..........................................................................101
Switching Waveforms ........................................................................................77
Table 22. Key to Switching Waveforms ................................. 77
Figure 10. Input Waveforms and Measurement Levels............. 77
FUNCTIONAL DESCRIPTION (Continued) . 102
CLK Input Function ..........................................................................................102
ADV# Input Function .......................................................................................102
WAIT# Output Function ................................................................................102
V
CC
Power-up ..................................................................................................... 78
Pin Capacitance .................................................................................................. 78
Figure 11. V
CC
Power-up Diagram ........................................ 78
AC Characteristics—Synchronous . . . . . . . . . . . 79
CLK Characterization ........................................................................................79
Figure 12. CLK Characterization ........................................... 79
FUNCTIONAL DESCRIPTION (Continued) . . 103
Latency ..................................................................................................................103
FUNCTIONAL DESCRIPTION (Continued) . 104
Address Latch by ADV# .................................................................................104
Burst Length ........................................................................................................104
Single Write .........................................................................................................104
Write Control ....................................................................................................105
Synchronous/Burst Read @ V
IO
= 1.8 V ..................................................... 80
Timing Diagrams .................................................................................................. 81
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK).
....................................................................................... 81
Figure 14. Synchronous Burst Mode Read.............................. 82
Figure 15. Eight-word Linear Burst with Wrap Around ............. 82
Figure 16. Eight-word Linear Burst without Wrap Around......... 83
Figure 17. Linear Burst with RDY Set One Cycle Before Data.... 83
FUNCTIONAL DESCRIPTION (Continued) . 106
Burst Read Suspend ..........................................................................................106
Burst Write Suspend ........................................................................................106
FUNCTIONAL DESCRIPTION (Continued) . . 107
Burst Read Termination ..................................................................................107
Burst Write Termination ................................................................................107
AC Characteristics—Asynchronous . . . . . . . . . . 84
Asynchronous Mode Read @ V
IO
pS = 1.8 V ............................................. 84
Timing Diagrams ................................................................................................. 84
Figure 18. Asynchronous Mode Read with Latched Addresses... 84
Figure 19. Asynchronous Mode Read..................................... 85
Hardware Reset (RESET#) .............................................................................. 85
Figure 20. Reset Timings..................................................... 85
ABSOLUTE MAXIMUM RATINGS (See
WARNING below.) . . . . . . . . . . . . . . . . . . . . . . 108
RECOMMENDED OPERATING CONDITIONS
(See WARNING below.) . . . . . . . . . . . . . . . . . . 108
(Referenced to VSS)
................................................................................... 108
Erase/Program Operations @ V
IO
= 1.8 V ................................................. 86
Figure 21. Asynchronous Program Operation Timings: WE#
Latched Addresses ............................................................. 87
DC CHARACTERISTICS
. . . . . (Under Recommended Operating Conditions
unless otherwise noted) . . . . . . . . Note *1,*2,*3 109
S71WS512NE0BFWZZ_00_A1 June 28, 2004
4
A d v a n c e
I n f o r m a t i o n
AC CHARACTERISTICS
(Under Recommended Operating Conditions
unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 110
ASYNCHRONOUS READ OPERATION (PAGE MODE) ................110
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 124
Asynchronous Read / Write Timing #1-1 (CE#1 Control) ...................124
Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control)
..................................................................................................................................124
AC CHARACTERISTICS (Continued) . . . . . . . . 111
ASYNCHRONOUS WRITE OPERATION ............................................. 111
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 125
Asynchronous Read / Write Timing #2 (OE#, WE# Control) ........125
Asynchronous Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
..................................................................................................................................125
AC CHARACTERISTICS (Continued) . . . . . . . . 112
SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE)
.................................................................................................................................. 112
SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE)
.................................................................................................................................. 112
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 126
Clock Input Timing ..........................................................................................126
Address Latch Timing (Synchronous Mode) ............................................126
AC CHARACTERISTICS (Continued) . . . . . . . . 113
SYNCHRONOUS READ OPERATION (BURST MODE) ................ 113
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 127
Synchronous Read Timing #1 (OE# Control) .........................................127
AC CHARACTERISTICS (Continued) . . . . . . . . 114
SYNCHRONOUS WRITE OPERATION (BURST MODE) .............. 114
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 128
Synchronous Read Timing #2 (CE#1 Control) ........................................128
AC CHARACTERISTICS (Continued) . . . . . . . . 115
POWER DOWN PARAMETERS ............................................................... 115
OTHER TIMING PARAMETERS ................................................................. 115
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 129
Synchronous Read Timing #3 (ADV# Control) .....................................129
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 130
Synchronous Write Timing #1 (WE# Level Control) ...........................130
AC CHARACTERISTICS (Continued) . . . . . . . . 116
AC TEST CONDITIONS ............................................................................... 116
AC MEASUREMENT OUTPUT LOAD CIRCUIT ................................. 116
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 131
Synchronous Write Timing #2 (WE# Single Clock Pulse Control) .. 131
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 117
Asynchronous Read Timing #1-1 (Basic Timing) ...................................... 117
Asynchronous Read Timing #1-2 (Basic Timing) ...................................... 117
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 132
Synchronous Write Timing #3 (ADV# Control) ...................................132
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 133
Synchronous Write Timing #4 (WE# Level Control, Single Write) 133
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 118
Asynchronous Read Timing #2 (OE# & Address Access) ...................118
Asynchronous Read Timing #3 (LB# / UB# Byte Access) ..................118
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 134
Synchronous Read to Write Timing #1(CE#1 Control) .......................134
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 119
Asynchronous Read Timing #4 (Page Address Access after CE#1 Control
Access) .................................................................................................................. 119
Asynchronous Read Timing #5 (Random and Page Address Access) 119
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 135
Synchronous Read to Write Timing #2(ADV# Control) .................... 135
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 136
Synchronous Write to Read Timing #1 (CE#1 Control) ......................136
TIMING DIAGRAMS (Continued) . . . . . . . . . . 120
Asynchronous Write Timing #1-1 (Basic Timing) ...................................120
Asynchronous Write Timing #1-2 (Basic Timing) ...................................120
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 137
Synchronous Write to Read Timing #2 (ADV# Control) .................. 137
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 121
Asynchronous Write Timing #2 (WE# Control) ................................... 121
Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Con-
trol) ........................................................................................................................ 121
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 138
POWER-UP Timing #1 ....................................................................................138
POWER-UP Timing #2 ...................................................................................138
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 139
POWER DOWN Entry and Exit Timing ..................................................139
Standby Entry Timing after Read or Write ..............................................139
TIMING DIAGRAMS (Continued) . . . . . . . . . . 122
Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Con-
trol) ....................................................................................................................... 122
Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Con-
trol) ....................................................................................................................... 122
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 140
Configuration Register Set Timing #1 (Asynchronous Operation) ...140
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 141
Configuration Register Set Timing #2 (Synchronous Operation) .....141
TIMING DIAGRAMS (Continued) . . . . . . . . . . 123
Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Con-
trol) ....................................................................................................................... 123
Revision Summary
June 28, 2004 S71WS512NE0BFWZZ_00_A1
5
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